Lines Matching refs:SHIFT_U32
90 SHIFT_U32(0x3F, BS_CCM_CCR_REG_BYPASS_COUNT)
92 #define BM_CCM_CCR_WB_COUNT SHIFT_U32(0x7, BS_CCM_CCR_WB_COUNT)
94 #define BM_CCM_CCR_OSCNT SHIFT_U32(0xFF, BS_CCM_CCR_OSCNT)
95 #define CCM_CCR_COSC_EN SHIFT_U32((1 << 12), BS_CCM_CCR_OSCNT)
135 #define BM_CCM_CACRR_ARM_PODF SHIFT_U32(0x7, BS_CCM_CACRR_ARM_PODF)
140 SHIFT_U32(0x7, BS_CCM_CBCDR_PERIPH_CLK2_PODF)
147 SHIFT_U32(0x7, BS_CCM_CBCDR_MMDC_CH0_PODF)
149 #define BM_CCM_CBCDR_AXI_PODF SHIFT_U32(0x7, BS_CCM_CBCDR_AXI_PODF)
151 #define BM_CCM_CBCDR_AHB_PODF SHIFT_U32(0x7, BS_CCM_CBCDR_AHB_PODF)
153 #define BM_CCM_CBCDR_IPG_PODF SHIFT_U32(0x3, BS_CCM_CBCDR_IPG_PODF)
160 SHIFT_U32(0x7, BS_CCM_CBCDR_MMDC_CH1_PODF)
163 SHIFT_U32(0x7, BS_CCM_CBCDR_PERIPH2_CLK2_PODF)
168 SHIFT_U32(0x7, BS_CCM_CBCMR_GPU3D_SHADER_PODF)
171 SHIFT_U32(0x7, BS_CCM_CBCMR_GPU3D_CORE_PODF)
174 SHIFT_U32(0x7, BS_CCM_CBCMR_GPU2D_CORE_PODF)
177 SHIFT_U32(0x3, BS_CCM_CBCMR_PRE_PERIPH2_CLK_SEL)
183 SHIFT_U32(0x3, BS_CCM_CBCMR_PRE_PERIPH_CLK_SEL)
186 SHIFT_U32(0x3, BS_CCM_CBCMR_GPU2D_CLK_SEL)
189 SHIFT_U32(0x3, BS_CCM_CBCMR_VPU_AXI_CLK_SEL)
192 SHIFT_U32(0x3, BS_CCM_CBCMR_PERIPH_CLK2_SEL)
199 SHIFT_U32(0x3, BS_CCM_CBCMR_GPU3D_SHADER_CLK_SEL)
202 SHIFT_U32(0x3, BS_CCM_CBCMR_GPU3D_CORE_CLK_SEL)
213 SHIFT_U32(0x3, BS_CCM_CSCMR1_ACLK_EMI_SLOW)
215 #define BM_CCM_CSCMR1_ACLK_EMI SHIFT_U32(0x3, BS_CCM_CSCMR1_ACLK_EMI)
218 SHIFT_U32(0x7, BS_CCM_CSCMR1_ACLK_EMI_SLOW_PODF)
221 SHIFT_U32(0x7, BS_CCM_CSCMR1_ACLK_EMI_PODF)
236 SHIFT_U32(0x3, BS_CCM_CSCMR1_SSI3_CLK_SEL)
239 SHIFT_U32(0x3, BS_CCM_CSCMR1_SSI2_CLK_SEL)
242 SHIFT_U32(0x3, BS_CCM_CSCMR1_SSI1_CLK_SEL)
245 SHIFT_U32(0x3F, BS_CCM_CSCMR1_PERCLK_PODF)
250 SHIFT_U32(0x3, BS_CCM_CSCMR2_ESAI_PRE_SEL)
257 SHIFT_U32(0x3F, BS_CCM_CSCMR2_CAN_CLK_SEL)
262 SHIFT_U32(0x7, BS_CCM_CSCDR1_VPU_AXI_PODF)
265 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC4_PODF)
268 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC3_PODF)
271 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC2_PODF)
274 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC1_PODF)
277 SHIFT_U32(0x7, BS_CCM_CSCDR1_USBOH3_CLK_PRED)
280 SHIFT_U32(0x3, BS_CCM_CSCDR1_USBOH3_CLK_PODF)
285 #define BM_CCM_CSCDR1_UART_CLK_PODF SHIFT_U32(0x1F, BS_CCM_CSCDR1_UA)
289 SHIFT_U32(0x3F, BS_CCM_CSCDR1_UART_CLK_PODF)
295 SHIFT_U32(0x3F, BS_CCM_CS1CDR_ESAI_CLK_PODF)
297 #define BM_CCM_CS1CDR_SSI3_CLK_PODF SHIFT_U32(0x3F, BS_CCM_CS1CDR_SSI3)
300 SHIFT_U32(0x3, BS_CCM_CS1CDR_ESAI_CLK_PRED)
303 SHIFT_U32(0x7, BS_CCM_CS1CDR_SSI1_CLK_PRED)
306 SHIFT_U32(0x3F, BS_CCM_CS1CDR_SSI1_CLK_PODF)
311 SHIFT_U32(0x3F, BS_CCM_CS2CDR_ENFC_CLK_PODF)
313 (SHIFT_U32(v, BS_CCM_CS2CDR_ENFC_CLK_PODF) & \
317 SHIFT_U32(0x7, BS_CCM_CS2CDR_ENFC_CLK_PRED)
319 (SHIFT_U32(v, BS_CCM_CS2CDR_ENFC_CLK_PRED) & \
323 SHIFT_U32(0x3, BS_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
325 (SHIFT_U32(v, BS_CCM_CS2CDR_ENFC_CLK_SEL) & \
329 SHIFT_U32(0x7, BS_CCM_CS2CDR_LDB_DI1_CLK_SEL)
332 SHIFT_U32(0x7, BS_CCM_CS2CDR_LDB_DI0_CLK_SEL)
335 SHIFT_U32(0x7, BS_CCM_CS2CDR_SSI2_CLK_PRED)
338 SHIFT_U32(0x3F, BS_CCM_CS2CDR_SSI2_CLK_PODF)
343 SHIFT_U32(0x7, BS_CCM_CDCDR_HSI_TX_PODF)
346 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF0_CLK_PRED)
352 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF0_CLK_PODF)
355 SHIFT_U32(0x3, BS_CCM_CDCDR_SPDIF0_CLK_SEL)
358 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF1_CLK_PRED)
361 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF1_CLK_PODF)
364 SHIFT_U32(0x3, BS_CCM_CDCDR_SPDIF1_CLK_SEL)
369 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL)
372 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI1_PODF)
375 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI1_CLK_SEL)
378 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL)
381 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI0_PODF)
384 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI0_CLK_SEL)
393 SHIFT_U32(0x3F, BS_CCM_CSCDR2_ECSPI_CLK_PODF)
396 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL)
399 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI1_PODF)
402 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI1_CLK_SEL)
405 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL)
408 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI0_PODF)
411 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI0_CLK_SEL)
416 SHIFT_U32(0x7, BS_CCM_CSCDR3_IPU2_HSP_PODF)
419 SHIFT_U32(0x3, BS_CCM_CSCDR3_IPU2_HSP_CLK_SEL)
422 SHIFT_U32(0x7, BS_CCM_CSCDR3_IPU1_HSP_PODF)
425 SHIFT_U32(0x3, BS_CCM_CSCDR3_IPU1_HSP_CLK_SEL)
486 SHIFT_U32(0x3, BS_CCM_CLPCR_STBY_COUNT)
501 SHIFT_U32(0x3, BS_CCM_CLPCR_LPSR_CLK_SEL)
507 SHIFT_U32(0x3, BS_CCM_CLPCR_LPM)
573 SHIFT_U32(0x7, BS_CCM_CCOSR_CKO2_DIV)
576 SHIFT_U32(0x1F, BS_CCM_CCOSR_CKO2_SEL)
585 SHIFT_U32(0x7, BS_CCM_CCOSR_CKOL_DIV)
588 SHIFT_U32(0xF, BS_CCM_CCOSR_CKOL_SEL)
607 SHIFT_U32(3, BS_CCM_CCGR0_AIPS_TZ1)
610 SHIFT_U32(3, BS_CCM_CCGR0_AIPS_TZ2)
613 SHIFT_U32(3, BS_CCM_CCGR0_APBHDMA)
616 SHIFT_U32(3, BS_CCM_CCGR0_ASRC)
619 SHIFT_U32(3, BS_CCM_CCGR0_CAAM_SECURE_MEM)
622 SHIFT_U32(3, BS_CCM_CCGR0_CAAM_WRAPPER_ACLK)
625 SHIFT_U32(3, BS_CCM_CCGR0_CAAM_WRAPPER_IPG)
627 #define BM_CCM_CCGR0_CAN1 SHIFT_U32(3, BS_CCM_CCGR0_CAN1)
630 SHIFT_U32(3, BS_CCM_CCGR0_CAN1_SERIAL)
632 #define BM_CCM_CCGR0_CAN2 SHIFT_U32(3, BS_CCM_CCGR0_CAN2)
635 SHIFT_U32(3, BS_CCM_CCGR0_CAN2_SERIAL)
638 SHIFT_U32(3, BS_CCM_CCGR0_CHEETAH_DBG_CLK)
640 #define BM_CCM_CCGR0_DCIC1 SHIFT_U32(3, BS_CCM_CCGR0_DCIC1)
642 #define BM_CCM_CCGR0_DCIC2 SHIFT_U32(3, BS_CCM_CCGR0_DCIC2)
644 #define BM_CCM_CCGR0_DTCP SHIFT_U32(3, BS_CCM_CCGR0_DTCP)
647 #define BM_CCM_CCGR1_ECSPI1S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI1S)
649 #define BM_CCM_CCGR1_ECSPI2S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI2S)
651 #define BM_CCM_CCGR1_ECSPI3S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI3S)
653 #define BM_CCM_CCGR1_ECSPI4S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI4S)
655 #define BM_CCM_CCGR1_ECSPI5S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI5S)
660 #define BM_CCM_CCGR1_EPIT1S SHIFT_U32(3, BS_CCM_CCGR1_EPIT1S)
662 #define BM_CCM_CCGR1_EPIT2S SHIFT_U32(3, BS_CCM_CCGR1_EPIT2S)
664 #define BM_CCM_CCGR1_ESAIS SHIFT_U32(3, BS_CCM_CCGR1_ESAIS)
666 #define BM_CCM_CCGR1_GPT_BUS SHIFT_U32(3, BS_CCM_CCGR1_GPT_BUS)
668 #define BM_CCM_CCGR1_GPT_SERIAL SHIFT_U32(3, BS_CCM_CCGR1_GPT_SERIAL)
670 #define BM_CCM_CCGR1_GPU2D SHIFT_U32(3, BS_CCM_CCGR1_GPU2D)
672 #define BM_CCM_CCGR1_GPU3D SHIFT_U32(3, BS_CCM_CCGR1_GPU3D)
676 SHIFT_U32(3, BS_CCM_CCGR2_HDMI_TX_IAHBCLK)
679 SHIFT_U32(3, BS_CCM_CCGR2_HDMI_TX_ISFRCLK)
681 #define BM_CCM_CCGR2_I2C1_SERIAL SHIFT_U32(3, BS_CCM_CCGR2_I2C1_SERIAL)
683 #define BM_CCM_CCGR2_I2C2_SERIAL SHIFT_U32(3, BS_CCM_CCGR2_I2C2_SERIAL)
685 #define BM_CCM_CCGR2_I2C3_SERIAL SHIFT_U32(3, BS_CCM_CCGR2_I2C3_SERIAL)
687 #define BM_CCM_CCGR2_OCOTP_CTRL SHIFT_U32(3, BS_CCM_CCGR2_OCOTP_CTRL)
690 SHIFT_U32(3, BS_CCM_CCGR2_IOMUX_IPT_CLK_IO)
692 #define BM_CCM_CCGR2_IPMUX1 SHIFT_U32(3, BS_CCM_CCGR2_IPMUX1)
694 #define BM_CCM_CCGR2_IPMUX2 SHIFT_U32(3, BS_CCM_CCGR2_IPMUX2)
696 #define BM_CCM_CCGR2_IPMUX3 SHIFT_U32(3, BS_CCM_CCGR2_IPMUX3)
699 SHIFT_U32(3, BS_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS)
702 SHIFT_U32(3, BS_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG)
705 SHIFT_U32(3, BS_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK)
708 #define BM_CCM_CCGR3_IPU1_IPU SHIFT_U32(3, BS_CCM_CCGR3_IPU1_IPU)
710 #define BM_CCM_CCGR3_IPU1_IPU_DI0 SHIFT_U32(3, BS_CCM_CCGR3_IPU1_IPU_DI0)
712 #define BM_CCM_CCGR3_IPU1_IPU_DI1 SHIFT_U32(3, BS_CCM_CCGR3_IPU1_IPU_DI1)
714 #define BM_CCM_CCGR3_IPU2_IPU SHIFT_U32(3, BS_CCM_CCGR3_IPU2_IPU)
716 #define BM_CCM_CCGR3_IPU2_IPU_DI0 SHIFT_U32(3, BS_CCM_CCGR3_IPU2_IPU_DI0)
718 #define BM_CCM_CCGR3_IPU2_IPU_DI1 SHIFT_U32(3, BS_CCM_CCGR3_IPU2_IPU_DI1)
720 #define BM_CCM_CCGR3_LDB_DI0 SHIFT_U32(3, BS_CCM_CCGR3_LDB_DI0)
722 #define BM_CCM_CCGR3_LDB_DI1 SHIFT_U32(3, BS_CCM_CCGR3_LDB_DI1)
725 SHIFT_U32(3, BS_CCM_CCGR3_MIPI_CORE_CFG)
727 #define BM_CCM_CCGR3_MLB SHIFT_U32(3, BS_CCM_CCGR3_MLB)
730 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0)
733 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1)
736 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0)
739 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1)
741 #define BM_CCM_CCGR3_OCRAM SHIFT_U32(3, BS_CCM_CCGR3_OCRAM)
744 SHIFT_U32(3, BS_CCM_CCGR3_OPENVGAXICLK)
747 #define BM_CCM_CCGR4_PCIE SHIFT_U32(3, BS_CCM_CCGR4_PCIE)
750 SHIFT_U32(3, BS_CCM_CCGR4_PL301_MX6QFAST1_S133)
753 SHIFT_U32(3, BS_CCM_CCGR4_PL301_MX6QPER1_BCH)
756 SHIFT_U32(3, BS_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE)
759 SHIFT_U32(3, BS_CCM_CCGR4_PWM1)
762 SHIFT_U32(3, BS_CCM_CCGR4_PWM2)
765 SHIFT_U32(3, BS_CCM_CCGR4_PWM3)
768 SHIFT_U32(3, BS_CCM_CCGR4_PWM4)
771 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB)
774 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH)
777 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO)
780 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB)
783 #define BM_CCM_CCGR5_ROM SHIFT_U32(3, BS_CCM_CCGR5_ROM)
785 #define BM_CCM_CCGR5_SATA SHIFT_U32(3, BS_CCM_CCGR5_SATA)
787 #define BM_CCM_CCGR5_SDMA SHIFT_U32(3, BS_CCM_CCGR5_SDMA)
789 #define BM_CCM_CCGR5_SPBA SHIFT_U32(3, BS_CCM_CCGR5_SPBA)
791 #define BM_CCM_CCGR5_SPDIF SHIFT_U32(3, BS_CCM_CCGR5_SPDIF)
793 #define BM_CCM_CCGR5_SSI1 SHIFT_U32(3, BS_CCM_CCGR5_SSI1)
795 #define BM_CCM_CCGR5_SSI2 SHIFT_U32(3, BS_CCM_CCGR5_SSI2)
797 #define BM_CCM_CCGR5_SSI3 SHIFT_U32(3, BS_CCM_CCGR5_SSI3)
799 #define BM_CCM_CCGR5_UART SHIFT_U32(3, BS_CCM_CCGR5_UART)
801 #define BM_CCM_CCGR5_UART_SERIAL SHIFT_U32(3, BS_CCM_CCGR5_UART_SERIAL)
804 #define BM_CCM_CCGR6_USBOH3 SHIFT_U32(3, BS_CCM_CCGR6_USBOH3)
806 #define BM_CCM_CCGR6_USDHC1 SHIFT_U32(3, BS_CCM_CCGR6_USDHC1)
808 #define BM_CCM_CCGR6_USDHC2 SHIFT_U32(3, BS_CCM_CCGR6_USDHC2)
810 #define BM_CCM_CCGR6_USDHC3 SHIFT_U32(3, BS_CCM_CCGR6_USDHC3)
812 #define BM_CCM_CCGR6_USDHC4 SHIFT_U32(3, BS_CCM_CCGR6_USDHC4)
814 #define BM_CCM_CCGR6_EMI_SLOW SHIFT_U32(3, BS_CCM_CCGR6_EMI_SLOW)
816 #define BM_CCM_CCGR6_VDOAXICLK SHIFT_U32(3, BS_CCM_CCGR6_VDOAXICLK)
818 #define BM_CCM_CCGR6_I2C4_SERIAL SHIFT_U32(3, BS_CCM_CCGR6_I2C4_SERIAL)
831 SHIFT_U32(0x3, BS_CCM_ANALOG_PLL_BYPASS_CLK_SRC)
833 (SHIFT_U32(clk, BS_CCM_ANALOG_PLL_BYPASS_CLK_SRC) & \
858 SHIFT_U32(0x7F, BS_CCM_ANALOG_PLL_DIV_SELECT)