Lines Matching refs:r0
23 str r2, [r0], #4
24 str sp, [r0], #4
25 str lr, [r0], #4
32 str sp, [r0], #4
33 str lr, [r0], #4
43 stm r0!, {r2}
48 stm r0!, {r2}
56 ldr r2, [r0], #4
57 ldr sp, [r0], #4
58 ldr lr, [r0], #4
67 ldr sp, [r0], #4
68 ldr lr, [r0], #4
77 ldm r0!, {r2}
82 ldm r0!, {r2}
99 push {r0-r7}
116 add r0, sp, #SM_CTX_SEC
125 ldm r8, {r0-r4}
127 cmp r0, r9
132 add r0, sp, #SM_CTX_NSEC
139 add r0, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R8)
140 ldm r0, {r8-r12}
158 read_scr r0
159 orr r0, r0, #(SCR_NS | SCR_FIQ) /* Set NS and FIQ bit in SCR */
160 write_scr r0
181 add r0, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R8)
182 stm r0, {r8-r12}
184 mov r0, sp
186 cmp r0, #SM_EXIT_TO_NON_SECURE
195 pop {r0-r7}
212 push {r0-r7}
230 add r0, sp, #SM_CTX_NSEC
232 add r0, sp, #(SM_CTX_NSEC + SM_NSEC_CTX_R8)
233 stm r0!, {r8-r12}
236 ldr r0, =vector_fiq_entry
237 str r0, [sp, #(SM_CTX_SEC + SM_SEC_CTX_MON_LR)]
240 add r0, sp, #SM_CTX_SEC
336 sub sp, r0, #(SM_CTX_SIZE - SM_CTX_SEC_END)
339 read_scr r0
340 orr r0, r0, #SCR_NS /* Set NS bit in SCR */
341 write_scr r0
364 bic r0, r0, #SCR_NS /* Clr NS bit in SCR */
365 write_scr r0
369 read_pmcr r0
370 orr r0, #PMCR_DP
371 write_pmcr r0
395 ldreq r0, =sm_vect_table_bpiall
400 ldreq r0, =sm_vect_table_a15
404 1: ldr r0, =sm_vect_table
405 2: write_mvbar r0
420 add r0, sp, #(SM_CTX_NSEC - SM_CTX_SEC_END)