Lines Matching refs:instruction
46 …pifunc{seL4\_TCB\_WriteRegisters}{tcb_writeregisters} with an initial stack pointer and instruction
444 Breakpoints, watchpoints, trace-events and instruction-performance sampling
465 Cortex~A7 for example, there are 6 exclusive instruction breakpoint registers,
468 The instruction breakpoint registers will always be assigned the lower API-IDs,
477 capable of generating a fault \textbf{only} on instruction execution. Currently this will be
479 in \texttt{seL4\_FirstBreakpoint}. If there are no instruction-break exclusive
492 supports both instruction and data breaks. Currently this will be set only on
505 \reg{Breakpoint instruction address} & \ipcbloc{IPCBuffer[0]} \\
524 an instruction breakpoint, to use when setting up the single-stepping
557 \reg{Breakpoint instruction address} & \texttt{num\_instructions} to skip & \ipcbloc{IPCBuffer[0]} …
600 …Instruction fault (1 if the fault was caused by an instruction fetch). & \ipcbloc{seL4\_VMFault\_P…