Lines Matching refs:intc_regs
13 intc_regs->bfDisableIRQs[0] = 0xffffffff; in initIRQController()
14 intc_regs->bfDisableIRQs[1] = 0xffffffff; in initIRQController()
15 intc_regs->bfDisableBasicIRQs = 0xffffffff; in initIRQController()
17 intc_regs->FIQ_control &= ~FIQCTRL_FIQ_ENABLE; in initIRQController()
19 intc_regs->bfEnableBasicIRQs = BIT(INTERRUPT_BASIC_IRQ_PENDING_REGISTER1 - BASIC_IRQ_OFFSET); in initIRQController()
20 intc_regs->bfEnableBasicIRQs = BIT(INTERRUPT_BASIC_IRQ_PENDING_REGISTER2 - BASIC_IRQ_OFFSET); in initIRQController()
47 pending = intc_regs->bfIRQBasicPending; in getActiveIRQ()
48 pending &= intc_regs->bfEnableBasicIRQs; in getActiveIRQ()
56 pending = intc_regs->bfGPUIRQPending[1]; in getActiveIRQ()
57 pending &= intc_regs->bfEnableIRQs[1]; in getActiveIRQ()
61 pending = intc_regs->bfGPUIRQPending[0]; in getActiveIRQ()
62 pending &= intc_regs->bfEnableIRQs[0]; in getActiveIRQ()
117 intc_regs->bfDisableBasicIRQs = BIT(irq - BASIC_IRQ_OFFSET); in maskInterrupt()
119 intc_regs->bfEnableBasicIRQs = BIT(irq - BASIC_IRQ_OFFSET); in maskInterrupt()
125 intc_regs->bfDisableIRQs[index] = BIT(normal_irq % 32); in maskInterrupt()
127 intc_regs->bfEnableIRQs[index] = BIT(normal_irq % 32); in maskInterrupt()