Lines Matching refs:inb
875 static Bit8u inb();
1149 inb(port)
1457 return inb(base_port + UART_LSR) & 0x20;
1469 while (!(inb(base_port + UART_LSR) & 0x40));
1804 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1810 if (inb(0x64) & 0x01) {
1811 inb(0x60);
1827 while ( (inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x00);
1832 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x01);
1836 if ((inb(0x60) != 0x55)){
1845 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x10);
1850 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x11);
1855 if ((inb(0x60) != 0x00)) {
1869 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x20);
1874 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x21);
1878 if ((inb(0x60) != 0xfa)) {
1884 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x31);
1887 if ((inb(0x60) != 0xaa)) {
1896 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x40);
1901 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x41);
1905 if ((inb(0x60) != 0xfa)) {
1914 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x50);
1922 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x60);
1930 while ((inb(0x64) & 0x02) && (--max>0)) outb(0x80, 0x70);
1935 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x71);
1939 if ((inb(0x60) != 0xfa)) {
2281 oldval = inb(0x92);
2543 status = inb(base+ATA_CB_STAT);
2640 sc = inb(iobase1+ATA_CB_SC);
2641 sn = inb(iobase1+ATA_CB_SN);
2651 sc = inb(iobase1+ATA_CB_SC);
2652 sn = inb(iobase1+ATA_CB_SN);
2654 cl = inb(iobase1+ATA_CB_CL);
2655 ch = inb(iobase1+ATA_CB_CH);
2656 st = inb(iobase1+ATA_CB_STAT);
2927 sc = inb(iobase1+ATA_CB_SC);
2928 sn = inb(iobase1+ATA_CB_SN);
2988 status = inb(iobase1 + ATA_CB_STAT);
3137 status = inb(iobase1 + ATA_CB_STAT);
3302 status = inb(iobase1 + ATA_CB_STAT);
3359 status = inb(iobase2 + ATA_CB_ASTAT);
3366 sc = inb(iobase1 + ATA_CB_SC);
3369 if(((inb(iobase1 + ATA_CB_SC)&0x7)==0x3) &&
3382 lcount = ((Bit16u)(inb(iobase1 + ATA_CB_CH))<<8)+inb(iobase1 + ATA_CB_CL);
3875 outb(addr+3, inb(addr+3) | 0x80);
3885 regs.u.r8.ah = inb(addr+5);
3886 regs.u.r8.al = inb(addr+6);
3891 while (((inb(addr+5) & 0x60) != 0x60) && (timeout)) {
3899 regs.u.r8.ah = inb(addr+5);
3905 while (((inb(addr+5) & 0x01) == 0) && (timeout)) {
3914 regs.u.r8.al = inb(addr);
3916 regs.u.r8.ah = inb(addr+5);
3921 regs.u.r8.ah = inb(addr+5);
3922 regs.u.r8.al = inb(addr+6);
3964 regs.u.r8.al = (inb(0x92) >> 1) & 0x01;
4011 irqDisable = inb( 0xA1 );
4893 while ((inb(0x64) & 0x01) == 0) outb(0x80, 0x21);
4894 if ((inb(0x60) == 0xfa)) {
4898 while ((inb(0x64) & 0x01) == 0) outb(0x80, 0x21);
4899 inb(0x60);
4963 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x00);
4965 if ((inb(0x60) == 0xfa)) {
4968 while ( ((inb(0x64) & 0x01) == 0) && (--max>0) ) outb(0x80, 0x00);
4971 kbd_code |= (inb(0x60) << 8);
5073 if ( inb(0x64) & 0x02 )
5076 while ( (inb(0x64) & 0x01) != 0x01 );
5077 prev_command_byte = inb(0x60);
5080 if ( inb(0x64) & 0x02 )
5095 if ( inb(0x64) & 0x02 )
5098 while ( (inb(0x64) & 0x01) != 0x01 );
5099 command_byte = inb(0x60);
5101 if ( inb(0x64) & 0x02 )
5116 if ( inb(0x64) & 0x02 )
5131 while ( (inb(0x64) & 0x21) != 0x21 ) {
5134 response = inb(0x60);
5145 if ( inb(0x64) & 0x02 )
5385 in_byte = inb(0x64);
5389 in_byte = inb(0x60);
5559 status = inb(read_word(ebda_seg, &EbdaData->ata.channels[device/2].iobase1) + ATA_CB_STAT);
6634 status = inb(0x1f7);
6653 status = inb(0x1f7);
6706 status = inb(0x1f7);
6712 status = inb(0x1f7);
6773 status = inb(0x1f7);
6795 status = inb(0x1f7);
6846 status = inb(0x1f7);
6852 status = inb(0x1f7);
6960 status = inb(0x01f7);
7096 val8 = inb(0x03f2);
7102 val8 = inb(0x3f4);
7117 prev_reset = inb(0x03f2) & 0x04;
7131 val8 = inb(0x3f4);
7555 val8 = inb(0x3f4);
7561 return_status[0] = inb(0x3f5);
7562 return_status[1] = inb(0x3f5);
7563 return_status[2] = inb(0x3f5);
7564 return_status[3] = inb(0x3f5);
7565 return_status[4] = inb(0x3f5);
7566 return_status[5] = inb(0x3f5);
7567 return_status[6] = inb(0x3f5);
7689 val8 = inb(0x3f4);
7695 return_status[0] = inb(0x3f5);
7696 return_status[1] = inb(0x3f5);
7697 return_status[2] = inb(0x3f5);
7698 return_status[3] = inb(0x3f5);
7699 return_status[4] = inb(0x3f5);
7700 return_status[5] = inb(0x3f5);
7701 return_status[6] = inb(0x3f5);
7849 val8 = inb(0x3f4);
7855 return_status[0] = inb(0x3f5);
7856 return_status[1] = inb(0x3f5);
7857 return_status[2] = inb(0x3f5);
7858 return_status[3] = inb(0x3f5);
7859 return_status[4] = inb(0x3f5);
7860 return_status[5] = inb(0x3f5);
7861 return_status[6] = inb(0x3f5);
8127 val8 = inb(0x03f4) & 0x80; // Main Status Register
8161 val8 = inb(addr+2);
8167 while (((inb(addr+1) & 0x40) == 0x40) && (timeout)) {
8172 val8 = inb(addr+2);
8179 val8 = inb(addr+1);
8541 outb(0xa1, inb(0xa1) & 0xfe); // enable IRQ 8