Lines Matching refs:r8
813 } r8;
837 } r8;
849 } r8;
853 #define SetCF(x) x.u.r8.flagsl |= 0x01
854 #define SetZF(x) x.u.r8.flagsl |= 0x40
855 #define ClearCF(x) x.u.r8.flagsl &= 0xfe
856 #define ClearZF(x) x.u.r8.flagsl &= 0xbf
857 #define GetCF(x) (x.u.r8.flagsl & 0x01)
3873 switch (regs.u.r8.ah) {
3876 if (regs.u.r8.al & 0xE0 == 0) {
3880 val16 = 0x600 >> ((regs.u.r8.al & 0xE0) >> 5);
3884 outb(addr+3, regs.u.r8.al & 0x1F);
3885 regs.u.r8.ah = inb(addr+5);
3886 regs.u.r8.al = inb(addr+6);
3898 if (timeout) outb(addr, regs.u.r8.al);
3899 regs.u.r8.ah = inb(addr+5);
3900 if (!timeout) regs.u.r8.ah |= 0x80;
3913 regs.u.r8.ah = 0;
3914 regs.u.r8.al = inb(addr);
3916 regs.u.r8.ah = inb(addr+5);
3921 regs.u.r8.ah = inb(addr+5);
3922 regs.u.r8.al = inb(addr+6);
3950 switch (regs.u.r8.ah) {
3952 switch (regs.u.r8.al) {
3956 regs.u.r8.ah = 0;
3961 regs.u.r8.ah = 0;
3964 regs.u.r8.al = (inb(0x92) >> 1) & 0x01;
3966 regs.u.r8.ah = 0;
3970 regs.u.r8.ah = 0;
3974 …_INFO("int15: Func 24h, subfunc %02xh, A20 gate control not supported\n", (unsigned) regs.u.r8.al);
3976 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
3982 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
3988 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
3997 regs.u.r8.ah = 0; // "ok ejection may proceed"
4001 if( regs.u.r8.al == 0 ) {
4019 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4021 } else if( regs.u.r8.al == 1 ) {
4030 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4031 regs.u.r8.al--;
4175 regs.u.r8.ah = 0;
4183 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4186 regs.u.r8.al = inb_cmos(0x30);
4187 regs.u.r8.ah = inb_cmos(0x31);
4209 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4215 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4219 regs.u.r8.ah = 0;
4232 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4239 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4259 switch (regs.u.r8.ah) {
4272 switch (regs.u.r8.al) {
4275 switch (regs.u.r8.bh) {
4284 regs.u.r8.ah = 0;
4291 regs.u.r8.ah = ret;
4301 regs.u.r8.ah = 5; // no far call installed
4311 regs.u.r8.ah = 0;
4316 regs.u.r8.ah = ret;
4320 BX_DEBUG_INT15("INT 15h C2 AL=0, BH=%02x\n", (unsigned) regs.u.r8.bh);
4322 regs.u.r8.ah = 1; // invalid subfunction
4330 if (regs.u.r8.al == 5) {
4331 if (regs.u.r8.bh != 3) {
4333 regs.u.r8.ah = 0x02; // invalid input
4337 mouse_flags_2 = (mouse_flags_2 & 0x00) | regs.u.r8.bh;
4362 regs.u.r8.ah = 0;
4363 regs.u.r8.bl = mouse_data1;
4364 regs.u.r8.bh = mouse_data2;
4373 regs.u.r8.ah = ret;
4378 switch (regs.u.r8.bh) {
4395 regs.u.r8.ah = 0;
4399 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4404 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4416 if (regs.u.r8.bh < 4) {
4422 ret = send_to_mouse_ctrl(regs.u.r8.bh);
4427 regs.u.r8.ah = 0;
4431 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4436 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4449 regs.u.r8.ah = 0;
4450 regs.u.r8.bh = mouse_data2;
4454 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4460 switch (regs.u.r8.bh) {
4476 regs.u.r8.ah = 0;
4477 regs.u.r8.bl = mouse_data1;
4478 regs.u.r8.cl = mouse_data2;
4479 regs.u.r8.dl = mouse_data3;
4490 regs.u.r8.ah = ret;
4497 if (regs.u.r8.bh == 1) {
4508 regs.u.r8.ah = 0;
4512 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4518 BX_PANIC("INT 15h C2 AL=6, BH=%02x\n", (unsigned) regs.u.r8.bh);
4542 regs.u.r8.ah = 0;
4547 regs.u.r8.ah = 1; // invalid function
4556 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4599 switch (regs.u.r8.ah) {
4645 switch(regs.u.r8.al)
4691 regs.u.r8.cl = inb_cmos(0x30);
4692 regs.u.r8.ch = inb_cmos(0x31);
4731 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
4844 regs.u.r8.cl = inb_cmos(0x30);
4845 regs.u.r8.ch = inb_cmos(0x31);
4854 regs.u.r8.dl = inb_cmos(0x34);
4855 regs.u.r8.dh = inb_cmos(0x35);
4871 regs.u.r8.ah = UNSUPPORTED_FUNCTION;
8157 if ((regs.u.r8.ah < 3) && (regs.u.r16.dx < 3) && (addr > 0)) {
8159 if (regs.u.r8.ah == 0) {
8160 outb(addr, regs.u.r8.al);
8171 if (regs.u.r8.ah == 1) {
8180 regs.u.r8.ah = (val8 ^ 0x48);
8181 if (!timeout) regs.u.r8.ah |= 0x01;
8402 switch (regs.u.r8.ah) {
8409 regs.u.r8.al = BiosData->midnight_flag;
8428 regs.u.r8.ah = 0;
8439 regs.u.r8.dh = inb_cmos(0x00); // Seconds
8440 regs.u.r8.cl = inb_cmos(0x02); // Minutes
8441 regs.u.r8.ch = inb_cmos(0x04); // Hours
8442 regs.u.r8.dl = inb_cmos(0x0b) & 0x01; // Stat Reg B
8443 regs.u.r8.ah = 0;
8444 regs.u.r8.al = regs.u.r8.ch;
8463 outb_cmos(0x00, regs.u.r8.dh); // Seconds
8464 outb_cmos(0x02, regs.u.r8.cl); // Minutes
8465 outb_cmos(0x04, regs.u.r8.ch); // Hours
8467 val8 = (inb_cmos(0x0b) & 0x60) | 0x02 | (regs.u.r8.dl & 0x01);
8470 regs.u.r8.ah = 0;
8471 regs.u.r8.al = val8; // val last written to Reg B
8476 regs.u.r8.ah = 0;
8481 regs.u.r8.cl = inb_cmos(0x09); // Year
8482 regs.u.r8.dh = inb_cmos(0x08); // Month
8483 regs.u.r8.dl = inb_cmos(0x07); // Day of Month
8484 regs.u.r8.ch = inb_cmos(0x32); // Century
8485 regs.u.r8.al = regs.u.r8.ch;
8505 outb_cmos(0x09, regs.u.r8.cl); // Year
8506 outb_cmos(0x08, regs.u.r8.dh); // Month
8507 outb_cmos(0x07, regs.u.r8.dl); // Day of Month
8508 outb_cmos(0x32, regs.u.r8.ch); // Century
8511 regs.u.r8.ah = 0;
8512 regs.u.r8.al = val8; // AL = val last written to Reg B
8538 outb_cmos(0x01, regs.u.r8.dh); // Seconds alarm
8539 outb_cmos(0x03, regs.u.r8.cl); // Minutes alarm
8540 outb_cmos(0x05, regs.u.r8.ch); // Hours alarm
8561 regs.u.r8.ah = 0;
8562 regs.u.r8.al = val8; // val last written to Reg B
8569 if (regs.u.r8.bl == 0xff) {
8571 } else if (regs.u.r8.bl == 0x81) {
8572 BX_INFO("unsupported PCI BIOS function 0x%02x\n", regs.u.r8.al);
8573 } else if (regs.u.r8.bl == 0x83) {
8575 } else if (regs.u.r8.bl == 0x86) {
8576 if (regs.u.r8.al == 0x02) {
8579 …BX_INFO("no PCI device with class code 0x%02x%04x found at index %d\n", regs.u.r8.cl, regs.u.r16.d…
8582 regs.u.r8.ah = regs.u.r8.bl;