Lines Matching refs:gc
40 int libxl__arch_domain_prepare_config(libxl__gc *gc, in libxl__arch_domain_prepare_config() argument
111 int libxl__arch_domain_save_config(libxl__gc *gc, in libxl__arch_domain_save_config() argument
130 int libxl__arch_domain_create(libxl__gc *gc, libxl_domain_config *d_config, in libxl__arch_domain_create() argument
136 int libxl__arch_extra_memory(libxl__gc *gc, in libxl__arch_extra_memory() argument
144 rc = libxl__get_acpi_size(gc, info, &size); in libxl__arch_extra_memory()
217 static int fdt_property_compat(libxl__gc *gc, void *fdt, unsigned nr_compat, ...) in fdt_property_compat() argument
234 p = compat = libxl__zalloc(gc, sz); in fdt_property_compat()
243 static int fdt_property_interrupts(libxl__gc *gc, void *fdt, in fdt_property_interrupts() argument
258 static int fdt_property_regs(libxl__gc *gc, void *fdt, in fdt_property_regs() argument
280 static int make_root_properties(libxl__gc *gc, in make_root_properties() argument
291 res = fdt_property_compat(gc, fdt, 2, in make_root_properties()
310 static int make_chosen_node(libxl__gc *gc, void *fdt, bool ramdisk, in make_chosen_node() argument
342 res = fdt_property_compat(gc, fdt, 2, "xen,guest-acpi", in make_chosen_node()
346 res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, in make_chosen_node()
360 static int make_cpus_node(libxl__gc *gc, void *fdt, int nr_cpus, in make_cpus_node() argument
387 res = fdt_property_compat(gc, fdt, 1, ainfo->cpu_compat); in make_cpus_node()
393 res = fdt_property_regs(gc, fdt, 1, 0, 1, mpidr_aff); in make_cpus_node()
406 static int make_psci_node(libxl__gc *gc, void *fdt) in make_psci_node() argument
413 res = fdt_property_compat(gc, fdt, 2, "arm,psci-0.2","arm,psci"); in make_psci_node()
431 static int make_memory_nodes(libxl__gc *gc, void *fdt, in make_memory_nodes() argument
449 res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, in make_memory_nodes()
460 static int make_gicv2_node(libxl__gc *gc, void *fdt, in make_gicv2_node() argument
470 res = fdt_property_compat(gc, fdt, 2, in make_gicv2_node()
485 res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, in make_gicv2_node()
503 static int make_gicv3_node(libxl__gc *gc, void *fdt) in make_gicv3_node() argument
515 res = fdt_property_compat(gc, fdt, 1, "arm,gic-v3"); in make_gicv3_node()
535 res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, in make_gicv3_node()
553 static int make_timer_node(libxl__gc *gc, void *fdt, in make_timer_node() argument
563 res = fdt_property_compat(gc, fdt, 1, ainfo->timer_compat); in make_timer_node()
570 res = fdt_property_interrupts(gc, fdt, ints, 3); in make_timer_node()
582 static int make_hypervisor_node(libxl__gc *gc, void *fdt, in make_hypervisor_node() argument
592 res = fdt_property_compat(gc, fdt, 2, in make_hypervisor_node()
600 res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, in make_hypervisor_node()
611 res = fdt_property_interrupts(gc, fdt, &intr, 1); in make_hypervisor_node()
620 static int make_vpl011_uart_node(libxl__gc *gc, void *fdt, in make_vpl011_uart_node() argument
630 res = fdt_property_compat(gc, fdt, 1, "arm,sbsa-uart"); in make_vpl011_uart_node()
633 res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, in make_vpl011_uart_node()
640 res = fdt_property_interrupts(gc, fdt, &intr, 1); in make_vpl011_uart_node()
652 static const struct arch_info *get_arch_info(libxl__gc *gc, in get_arch_info() argument
666 static void debug_dump_fdt(libxl__gc *gc, void *fdt) in debug_dump_fdt() argument
692 static int check_partial_fdt(libxl__gc *gc, void *fdt, size_t size) in check_partial_fdt() argument
715 static int copy_properties(libxl__gc *gc, void *fdt, void *pfdt, in copy_properties() argument
740 static int copy_node(libxl__gc *gc, void *fdt, void *pfdt, in copy_node() argument
748 r = copy_properties(gc, fdt, pfdt, nodeoff); in copy_node()
754 r = copy_node(gc, fdt, pfdt, nodeoff, depth + 1); in copy_node()
767 static int copy_node_by_path(libxl__gc *gc, const char *path, in copy_node_by_path() argument
790 r = copy_node(gc, fdt, pfdt, nodeoff, 0); in copy_node_by_path()
802 static int copy_partial_fdt(libxl__gc *gc, void *fdt, void *pfdt) in copy_partial_fdt() argument
806 r = copy_node_by_path(gc, "/passthrough", fdt, pfdt); in copy_partial_fdt()
812 r = copy_node_by_path(gc, "/aliases", fdt, pfdt); in copy_partial_fdt()
823 static int check_partial_fdt(libxl__gc *gc, void *fdt, size_t size) in check_partial_fdt() argument
830 static int copy_partial_fdt(libxl__gc *gc, void *fdt, void *pfdt) in copy_partial_fdt() argument
843 static int libxl__prepare_dtb(libxl__gc *gc, libxl_domain_build_info *info, in libxl__prepare_dtb() argument
862 ainfo = get_arch_info(gc, dom); in libxl__prepare_dtb()
879 libxl__ptr_add(gc, pfdt); in libxl__prepare_dtb()
881 if (check_partial_fdt(gc, pfdt, pfdt_size)) in libxl__prepare_dtb()
917 fdt = libxl__realloc(gc, fdt, fdt_size); in libxl__prepare_dtb()
925 FDT( make_root_properties(gc, vers, fdt) ); in libxl__prepare_dtb()
926 FDT( make_chosen_node(gc, fdt, !!dom->ramdisk_blob, state, info) ); in libxl__prepare_dtb()
927 FDT( make_cpus_node(gc, fdt, info->max_vcpus, ainfo) ); in libxl__prepare_dtb()
928 FDT( make_psci_node(gc, fdt) ); in libxl__prepare_dtb()
930 FDT( make_memory_nodes(gc, fdt, dom) ); in libxl__prepare_dtb()
934 FDT( make_gicv2_node(gc, fdt, in libxl__prepare_dtb()
939 FDT( make_gicv3_node(gc, fdt) ); in libxl__prepare_dtb()
948 FDT( make_timer_node(gc, fdt, ainfo, xc_config->clock_frequency) ); in libxl__prepare_dtb()
949 FDT( make_hypervisor_node(gc, fdt, vers) ); in libxl__prepare_dtb()
952 FDT( make_vpl011_uart_node(gc, fdt, ainfo, dom) ); in libxl__prepare_dtb()
955 FDT( copy_partial_fdt(gc, fdt, pfdt) ); in libxl__prepare_dtb()
979 int libxl__arch_domain_init_hw_description(libxl__gc *gc, in libxl__arch_domain_init_hw_description() argument
1001 rc = libxl__prepare_dtb(gc, info, state, dom); in libxl__arch_domain_init_hw_description()
1017 rc = libxl__prepare_acpi(gc, info, dom); in libxl__arch_domain_init_hw_description()
1023 static void finalise_one_node(libxl__gc *gc, void *fdt, const char *uname, in finalise_one_node() argument
1048 int libxl__arch_domain_finalise_hw_description(libxl__gc *gc, in libxl__arch_domain_finalise_hw_description() argument
1090 finalise_one_node(gc, fdt, "/memory", bankbase[i], size); in libxl__arch_domain_finalise_hw_description()
1094 finalise_one_node(gc, fdt, "/chosen/module", GUEST_ACPI_BASE, in libxl__arch_domain_finalise_hw_description()
1098 debug_dump_fdt(gc, fdt); in libxl__arch_domain_finalise_hw_description()
1103 int libxl__arch_build_dom_finish(libxl__gc *gc, in libxl__arch_build_dom_finish() argument
1130 int libxl__arch_vnuma_build_vmemrange(libxl__gc *gc, in libxl__arch_vnuma_build_vmemrange() argument
1135 return libxl__vnuma_build_vmemrange_pv_generic(gc, domid, info, state); in libxl__arch_vnuma_build_vmemrange()
1138 int libxl__arch_domain_map_irq(libxl__gc *gc, uint32_t domid, int irq) in libxl__arch_domain_map_irq() argument
1143 int libxl__arch_domain_construct_memmap(libxl__gc *gc, in libxl__arch_domain_construct_memmap() argument