Lines Matching refs:ldr
102 ldr r0, =start
108 ldr r8, =_sdtb
120 ldr r0, =start
142 ldr r0, =smp_up_cpu
145 2: ldr r1, [r0]
153 ldr r11, =EARLY_UART_BASE_ADDRESS /* r11 := UART base address */
189 ldr r0, =__bss_start /* Load start & end of bss */
190 ldr r1, =__bss_end
215 ldr r1, [r1, #PROCINFO_cpu_init] /* r1 := vaddr(init func) */
221 ldr r0, =MAIR0VAL
222 ldr r1, =MAIR1VAL
234 ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0))
247 ldr r0, =(HSCTLR_BASE|SCTLR_A)
270 ldr r4, =boot_pgtable
276 ldr r1, =boot_second
297 ldr r4, =boot_second
300 ldr r1, =boot_third
313 ldr r3, =LPAE_ENTRY_MASK
327 1: ldr r4, =boot_third
363 ldr r1, =paging /* Explicit vaddr, not RIP-relative */
386 ldr r1, =xen_fixmap /* r1 := vaddr (xen_fixmap) */
396 ldr r1, =boot_second /* r1 := vaddr (boot_second) */
397 ldr r2, =xen_fixmap
401 ldr r4, =FIXMAP_ADDR(0)
406 ldr r11, =EARLY_UART_VIRTUAL_ADDRESS
432 ldr r4, =init_ttbr /* VA of HTTBR value stashed by CPU 0 */
445 ldr r0, =init_data
447 ldr sp, [r0]
479 ldr r4, [sp, #8*4] /* Get 4th argument from stack */
507 ldr r6, =cacheline_bytes /* r6 := step */
508 ldr r6, [r6]
626 ldr r1, = __proc_info_start
628 ldr r2, = __proc_info_end
630 1: ldr r3, [r1, #PROCINFO_cpu_mask]
632 ldr r3, [r1, #PROCINFO_cpu_val] /* r3 := cpu val in current proc info */