Lines Matching refs:r0
62 adr r0, 98f ; \
86 mov r0, r0
102 ldr r0, =start
104 sub r10, r9, r0 /* r10 := phys-offset */
120 ldr r0, =start
122 sub r10, r9, r0 /* r10 := phys-offset */
142 ldr r0, =smp_up_cpu
143 add r0, r0, r10 /* Apply physical offset */
145 2: ldr r1, [r0]
157 mov r0, r7
163 mrc CP32(r0, ID_PFR1)
164 and r0, r0, #0xf000 /* Bits 12-15 define virt extensions */
165 teq r0, #0x1000 /* Must == 0x1 or may be incompatible */
172 mrs r0, cpsr
173 and r0, r0, #0x1f /* Mode is in the low 5 bits of CPSR */
174 teq r0, #0x1a /* Hyp Mode? */
189 ldr r0, =__bss_start /* Load start & end of bss */
191 add r0, r0, r10 /* Apply physical offset */
195 1: str r2, [r0], #4
196 cmp r0, r1
206 mov r4, r0
208 mov r0, r4
221 ldr r0, =MAIR0VAL
223 mcr CP32(r0, MAIR0)
225 mcr CP32(r0, HMAIR0)
234 ldr r0, =(TCR_RES1|TCR_SH0_IS|TCR_ORGN0_WBWA|TCR_IRGN0_WBWA|TCR_T0SZ(0))
235 mcr CP32(r0, HTCR)
247 ldr r0, =(HSCTLR_BASE|SCTLR_A)
248 mcr CP32(r0, HSCTLR)
364 mrc CP32(r0, HSCTLR)
365 orr r0, r0, #(SCTLR_M|SCTLR_C) /* Enable MMU and D-cache */
367 mcr CP32(r0, HSCTLR) /* now paging is enabled */
417 mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */
438 mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */
439 mcr CP32(r0, ICIALLU) /* Flush I-cache */
440 mcr CP32(r0, BPIALL) /* Flush branch predictor */
445 ldr r0, =init_data
446 add r0, #INITINFO_stack /* Find the boot-time stack */
447 ldr sp, [r0]
450 mov r0, r10 /* Marshal args: - phys_offset */
521 mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */
522 mcr CP32(r0, ICIALLU) /* Flush I-cache */
523 mcr CP32(r0, BPIALL) /* Flush branch predictor */
527 mcrr CP64(r0, r1, HTTBR)
533 mcr CP32(r0, TLBIALLH) /* Flush hypervisor TLB */
534 mcr CP32(r0, ICIALLU) /* Flush I-cache */
535 mcr CP32(r0, BPIALL) /* Flush branch predictor */
553 adr r0, 1f
566 ldrb r1, [r0], #1 /* Load next char */
583 and r2, r0, #0xf0000000 /* Mask off the top nybble */
586 lsl r0, #4 /* Roll it through one nybble at a time */
608 mov r0, r1
625 mrc CP32(r0, MIDR) /* r0 := our cpu id */
631 and r4, r0, r3 /* r4 := our cpu id with mask */