Lines Matching refs:READ_SYSREG32
253 val = READ_SYSREG32(ICC_SRE_EL2); in gicv3_enable_sre()
343 d->v3.apr0[2] = READ_SYSREG32(ICH_AP0R2_EL2); in save_aprn_regs()
344 d->v3.apr1[2] = READ_SYSREG32(ICH_AP1R2_EL2); in save_aprn_regs()
347 d->v3.apr0[1] = READ_SYSREG32(ICH_AP0R1_EL2); in save_aprn_regs()
348 d->v3.apr1[1] = READ_SYSREG32(ICH_AP1R1_EL2); in save_aprn_regs()
351 d->v3.apr0[0] = READ_SYSREG32(ICH_AP0R0_EL2); in save_aprn_regs()
352 d->v3.apr1[0] = READ_SYSREG32(ICH_AP1R0_EL2); in save_aprn_regs()
376 v->arch.gic.v3.vmcr = READ_SYSREG32(ICH_VMCR_EL2); in gicv3_save_state()
377 v->arch.gic.v3.sre_el1 = READ_SYSREG32(ICC_SRE_EL1); in gicv3_save_state()
384 val = READ_SYSREG32(ICC_SRE_EL2); in gicv3_restore_state()
471 unsigned int irq = READ_SYSREG32(ICC_IAR1_EL1); in gicv3_read_irq()
830 vtr = READ_SYSREG32(ICH_VTR_EL2); in gicv3_hyp_init()
861 hcr = READ_SYSREG32(ICH_HCR_EL2); in gicv3_hyp_disable()
1030 hcr = READ_SYSREG32(ICH_HCR_EL2); in gicv3_hcr_status()
1040 return ((READ_SYSREG32(ICH_VMCR_EL2) >> GICH_VMCR_PRIORITY_SHIFT) & in gicv3_read_vmcr_priority()
1051 return READ_SYSREG32(ICH_AP1R0_EL2); in gicv3_read_apr()
1054 return READ_SYSREG32(ICH_AP1R1_EL2); in gicv3_read_apr()
1057 return READ_SYSREG32(ICH_AP1R2_EL2); in gicv3_read_apr()