Lines Matching refs:v3
78 v->arch.gic.v3.lr[15] = READ_SYSREG(ICH_LR15_EL2); in gicv3_save_lrs()
80 v->arch.gic.v3.lr[14] = READ_SYSREG(ICH_LR14_EL2); in gicv3_save_lrs()
82 v->arch.gic.v3.lr[13] = READ_SYSREG(ICH_LR13_EL2); in gicv3_save_lrs()
84 v->arch.gic.v3.lr[12] = READ_SYSREG(ICH_LR12_EL2); in gicv3_save_lrs()
86 v->arch.gic.v3.lr[11] = READ_SYSREG(ICH_LR11_EL2); in gicv3_save_lrs()
88 v->arch.gic.v3.lr[10] = READ_SYSREG(ICH_LR10_EL2); in gicv3_save_lrs()
90 v->arch.gic.v3.lr[9] = READ_SYSREG(ICH_LR9_EL2); in gicv3_save_lrs()
92 v->arch.gic.v3.lr[8] = READ_SYSREG(ICH_LR8_EL2); in gicv3_save_lrs()
94 v->arch.gic.v3.lr[7] = READ_SYSREG(ICH_LR7_EL2); in gicv3_save_lrs()
96 v->arch.gic.v3.lr[6] = READ_SYSREG(ICH_LR6_EL2); in gicv3_save_lrs()
98 v->arch.gic.v3.lr[5] = READ_SYSREG(ICH_LR5_EL2); in gicv3_save_lrs()
100 v->arch.gic.v3.lr[4] = READ_SYSREG(ICH_LR4_EL2); in gicv3_save_lrs()
102 v->arch.gic.v3.lr[3] = READ_SYSREG(ICH_LR3_EL2); in gicv3_save_lrs()
104 v->arch.gic.v3.lr[2] = READ_SYSREG(ICH_LR2_EL2); in gicv3_save_lrs()
106 v->arch.gic.v3.lr[1] = READ_SYSREG(ICH_LR1_EL2); in gicv3_save_lrs()
108 v->arch.gic.v3.lr[0] = READ_SYSREG(ICH_LR0_EL2); in gicv3_save_lrs()
125 WRITE_SYSREG(v->arch.gic.v3.lr[15], ICH_LR15_EL2); in gicv3_restore_lrs()
127 WRITE_SYSREG(v->arch.gic.v3.lr[14], ICH_LR14_EL2); in gicv3_restore_lrs()
129 WRITE_SYSREG(v->arch.gic.v3.lr[13], ICH_LR13_EL2); in gicv3_restore_lrs()
131 WRITE_SYSREG(v->arch.gic.v3.lr[12], ICH_LR12_EL2); in gicv3_restore_lrs()
133 WRITE_SYSREG(v->arch.gic.v3.lr[11], ICH_LR11_EL2); in gicv3_restore_lrs()
135 WRITE_SYSREG(v->arch.gic.v3.lr[10], ICH_LR10_EL2); in gicv3_restore_lrs()
137 WRITE_SYSREG(v->arch.gic.v3.lr[9], ICH_LR9_EL2); in gicv3_restore_lrs()
139 WRITE_SYSREG(v->arch.gic.v3.lr[8], ICH_LR8_EL2); in gicv3_restore_lrs()
141 WRITE_SYSREG(v->arch.gic.v3.lr[7], ICH_LR7_EL2); in gicv3_restore_lrs()
143 WRITE_SYSREG(v->arch.gic.v3.lr[6], ICH_LR6_EL2); in gicv3_restore_lrs()
145 WRITE_SYSREG(v->arch.gic.v3.lr[5], ICH_LR5_EL2); in gicv3_restore_lrs()
147 WRITE_SYSREG(v->arch.gic.v3.lr[4], ICH_LR4_EL2); in gicv3_restore_lrs()
149 WRITE_SYSREG(v->arch.gic.v3.lr[3], ICH_LR3_EL2); in gicv3_restore_lrs()
151 WRITE_SYSREG(v->arch.gic.v3.lr[2], ICH_LR2_EL2); in gicv3_restore_lrs()
153 WRITE_SYSREG(v->arch.gic.v3.lr[1], ICH_LR1_EL2); in gicv3_restore_lrs()
155 WRITE_SYSREG(v->arch.gic.v3.lr[0], ICH_LR0_EL2); in gicv3_restore_lrs()
320 WRITE_SYSREG32(d->v3.apr0[2], ICH_AP0R2_EL2); in restore_aprn_regs()
321 WRITE_SYSREG32(d->v3.apr1[2], ICH_AP1R2_EL2); in restore_aprn_regs()
324 WRITE_SYSREG32(d->v3.apr0[1], ICH_AP0R1_EL2); in restore_aprn_regs()
325 WRITE_SYSREG32(d->v3.apr1[1], ICH_AP1R1_EL2); in restore_aprn_regs()
328 WRITE_SYSREG32(d->v3.apr0[0], ICH_AP0R0_EL2); in restore_aprn_regs()
329 WRITE_SYSREG32(d->v3.apr1[0], ICH_AP1R0_EL2); in restore_aprn_regs()
343 d->v3.apr0[2] = READ_SYSREG32(ICH_AP0R2_EL2); in save_aprn_regs()
344 d->v3.apr1[2] = READ_SYSREG32(ICH_AP1R2_EL2); in save_aprn_regs()
347 d->v3.apr0[1] = READ_SYSREG32(ICH_AP0R1_EL2); in save_aprn_regs()
348 d->v3.apr1[1] = READ_SYSREG32(ICH_AP1R1_EL2); in save_aprn_regs()
351 d->v3.apr0[0] = READ_SYSREG32(ICH_AP0R0_EL2); in save_aprn_regs()
352 d->v3.apr1[0] = READ_SYSREG32(ICH_AP1R0_EL2); in save_aprn_regs()
376 v->arch.gic.v3.vmcr = READ_SYSREG32(ICH_VMCR_EL2); in gicv3_save_state()
377 v->arch.gic.v3.sre_el1 = READ_SYSREG32(ICC_SRE_EL1); in gicv3_save_state()
403 WRITE_SYSREG32(v->arch.gic.v3.sre_el1, ICC_SRE_EL1); in gicv3_restore_state()
405 WRITE_SYSREG32(v->arch.gic.v3.vmcr, ICH_VMCR_EL2); in gicv3_restore_state()
427 printk(" VCPU_LR[%d]=%lx\n", i, v->arch.gic.v3.lr[i]); in gicv3_dump_state()