Lines Matching refs:seg
141 return !!(pci_conf_read16(dev->seg, bus, slot, func, PCI_COMMAND) & in memory_decoded()
147 u16 control = pci_conf_read16(dev->seg, dev->bus, PCI_SLOT(dev->devfn), in msix_memory_decoded()
202 u16 data, seg = dev->seg; in read_msi_msg() local
207 msg->address_lo = pci_conf_read32(seg, bus, slot, func, in read_msi_msg()
211 msg->address_hi = pci_conf_read32(seg, bus, slot, func, in read_msi_msg()
213 data = pci_conf_read16(seg, bus, slot, func, in read_msi_msg()
219 data = pci_conf_read16(seg, bus, slot, func, in read_msi_msg()
267 u16 seg = dev->seg; in write_msi_msg() local
277 pci_conf_write32(seg, bus, slot, func, msi_lower_address_reg(pos), in write_msi_msg()
281 pci_conf_write32(seg, bus, slot, func, msi_upper_address_reg(pos), in write_msi_msg()
283 pci_conf_write16(seg, bus, slot, func, msi_data_reg(pos, 1), in write_msi_msg()
287 pci_conf_write16(seg, bus, slot, func, msi_data_reg(pos, 0), in write_msi_msg()
337 void __msi_set_enable(u16 seg, u8 bus, u8 slot, u8 func, int pos, int enable) in __msi_set_enable() argument
339 u16 control = pci_conf_read16(seg, bus, slot, func, pos + PCI_MSI_FLAGS); in __msi_set_enable()
344 pci_conf_write16(seg, bus, slot, func, pos + PCI_MSI_FLAGS, control); in __msi_set_enable()
350 u16 seg = dev->seg; in msi_set_enable() local
355 pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); in msi_set_enable()
357 __msi_set_enable(seg, bus, slot, func, pos, enable); in msi_set_enable()
363 u16 control, seg = dev->seg; in msix_set_enable() local
368 pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSIX); in msix_set_enable()
371 control = pci_conf_read16(seg, bus, slot, func, msix_control_reg(pos)); in msix_set_enable()
375 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); in msix_set_enable()
390 u16 seg, control; in msi_set_mask_bit() local
397 seg = pdev->seg; in msi_set_mask_bit()
408 mask_bits = pci_conf_read32(seg, bus, slot, func, entry->msi.mpos); in msi_set_mask_bit()
411 pci_conf_write32(seg, bus, slot, func, entry->msi.mpos, mask_bits); in msi_set_mask_bit()
416 control = pci_conf_read16(seg, bus, slot, func, in msi_set_mask_bit()
421 pci_conf_write16(seg, bus, slot, func, in msi_set_mask_bit()
449 desc->irq, domid, pdev->seg, pdev->bus, in msi_set_mask_bit()
456 pci_conf_write16(seg, bus, slot, func, in msi_set_mask_bit()
478 return (pci_conf_read32(entry->dev->seg, entry->dev->bus, in msi_get_mask_bit()
597 control = pci_conf_read16(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), in setup_msi_irq()
600 pci_conf_write16(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), in setup_msi_irq()
611 pci_conf_write16(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), in setup_msi_irq()
692 u16 control, seg = dev->seg; in msi_capability_init() local
698 pos = pci_find_cap_offset(seg, bus, slot, func, PCI_CAP_ID_MSI); in msi_capability_init()
701 control = pci_conf_read16(seg, bus, slot, func, msi_control_reg(pos)); in msi_capability_init()
737 maskbits = pci_conf_read32(seg, bus, slot, func, mpos); in msi_capability_init()
739 pci_conf_write32(seg, bus, slot, func, mpos, maskbits); in msi_capability_init()
745 pci_conf_write16(seg, bus, slot, func, msi_control_reg(pos), control); in msi_capability_init()
750 static u64 read_pci_mem_bar(u16 seg, u8 bus, u8 slot, u8 func, u8 bir, int vf) in read_pci_mem_bar() argument
758 struct pci_dev *pdev = pci_get_pdev(seg, bus, PCI_DEVFN(slot, func)); in read_pci_mem_bar()
759 unsigned int pos = pci_find_ext_capability(seg, bus, in read_pci_mem_bar()
762 u16 ctrl = pci_conf_read16(seg, bus, slot, func, pos + PCI_SRIOV_CTRL); in read_pci_mem_bar()
763 u16 num_vf = pci_conf_read16(seg, bus, slot, func, in read_pci_mem_bar()
765 u16 offset = pci_conf_read16(seg, bus, slot, func, in read_pci_mem_bar()
767 u16 stride = pci_conf_read16(seg, bus, slot, func, in read_pci_mem_bar()
793 else switch ( pci_conf_read8(seg, bus, slot, func, in read_pci_mem_bar()
811 addr = pci_conf_read32(seg, bus, slot, func, base + bir * 4); in read_pci_mem_bar()
820 ((u64)pci_conf_read32(seg, bus, slot, func, in read_pci_mem_bar()
849 u16 seg = dev->seg; in msix_capability_init() local
857 control = pci_conf_read16(seg, bus, slot, func, msix_control_reg(pos)); in msix_capability_init()
865 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), in msix_capability_init()
871 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), in msix_capability_init()
881 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), in msix_capability_init()
889 table_offset = pci_conf_read32(seg, bus, slot, func, in msix_capability_init()
909 table_paddr = read_pci_mem_bar(seg, pbus, pslot, pfunc, bir, vf); in msix_capability_init()
915 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), in msix_capability_init()
936 pba_offset = pci_conf_read32(seg, bus, slot, func, in msix_capability_init()
939 pba_paddr = read_pci_mem_bar(seg, pbus, pslot, pfunc, bir, vf); in msix_capability_init()
959 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), in msix_capability_init()
1009 seg, bus, slot, func, d->domain_id); in msix_capability_init()
1023 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); in msix_capability_init()
1045 pdev = pci_get_pdev(msi->seg, msi->bus, msi->devfn); in __pci_enable_msi()
1053 msi->irq, msi->seg, msi->bus, in __pci_enable_msi()
1062 msi->seg, msi->bus, in __pci_enable_msi()
1105 pdev = pci_get_pdev(msi->seg, msi->bus, msi->devfn); in __pci_enable_msix()
1106 pos = pci_find_cap_offset(msi->seg, msi->bus, slot, func, PCI_CAP_ID_MSIX); in __pci_enable_msix()
1110 control = pci_conf_read16(msi->seg, msi->bus, slot, func, in __pci_enable_msix()
1120 msi->irq, msi->seg, msi->bus, in __pci_enable_msix()
1129 msi->seg, msi->bus, in __pci_enable_msix()
1153 u16 seg = dev->seg; in __pci_disable_msix() local
1157 unsigned int pos = pci_find_cap_offset(seg, bus, slot, func, in __pci_disable_msix()
1159 u16 control = pci_conf_read16(seg, bus, slot, func, in __pci_disable_msix()
1166 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), in __pci_disable_msix()
1179 entry->irq, dev->seg, dev->bus, in __pci_disable_msix()
1186 pci_conf_write16(seg, bus, slot, func, msix_control_reg(pos), control); in __pci_disable_msix()
1191 int pci_prepare_msix(u16 seg, u8 bus, u8 devfn, bool off) in pci_prepare_msix() argument
1196 unsigned int pos = pci_find_cap_offset(seg, bus, slot, func, in pci_prepare_msix()
1206 pdev = pci_get_pdev(seg, bus, devfn); in pci_prepare_msix()
1218 u16 control = pci_conf_read16(seg, bus, slot, func, in pci_prepare_msix()
1277 u16 seg = pdev->seg; in pci_msi_conf_write_intercept() local
1288 : pci_find_cap_offset(seg, bus, slot, func, in pci_msi_conf_write_intercept()
1320 cntl = pci_conf_read16(seg, bus, slot, func, msi_control_reg(pos)); in pci_msi_conf_write_intercept()
1357 (pdev->seg << 16) | (pdev->bus << 8) | in pci_restore_msi_state()
1378 pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), in pci_restore_msi_state()
1382 pci_conf_write16(pdev->seg, pdev->bus, slot, func, in pci_restore_msi_state()
1397 control = pci_conf_read16(pdev->seg, pdev->bus, slot, func, in pci_restore_msi_state()
1399 pci_conf_write16(pdev->seg, pdev->bus, slot, func, in pci_restore_msi_state()
1406 pci_conf_write16(pdev->seg, pdev->bus, slot, func, in pci_restore_msi_state()
1440 control = pci_conf_read16(pdev->seg, pdev->bus, slot, func, cpos) & in pci_restore_msi_state()
1443 pci_conf_write16(pdev->seg, pdev->bus, PCI_SLOT(pdev->devfn), in pci_restore_msi_state()
1451 pci_conf_write16(pdev->seg, pdev->bus, slot, func, in pci_restore_msi_state()