Lines Matching refs:val
44 #define CTRL_CLEAR(val) (val &= (1ULL<<21)) argument
45 #define CTRL_SET_ENABLE(val) (val |= 1ULL<<20) argument
46 #define CTRL_SET_USR(val,u) (val |= ((u & 1) << 16)) argument
47 #define CTRL_SET_KERN(val,k) (val |= ((k & 1) << 17)) argument
48 #define CTRL_SET_UM(val, m) (val |= ((m & 0xff) << 8)) argument
49 #define CTRL_SET_EVENT(val, e) (val |= (((e >> 8) & 0xf) | (e & 0xff))) argument
50 #define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 0x1ULL) << 41)) argument
51 #define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 0x1ULL) << 40)) argument
106 #define clamp(val, min, max) ({ \ argument
107 typeof(val) __val = (val); \
142 static inline u64 op_amd_randomize_ibs_op(u64 val) in op_amd_randomize_ibs_op() argument
160 val += (s8)(random >> 4); in op_amd_randomize_ibs_op()
162 val |= (u64)(random & IBS_RANDOM_MASK) << 32; in op_amd_randomize_ibs_op()
164 return val; in op_amd_randomize_ibs_op()
255 u64 val, ctl; in handle_ibs() local
264 rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); in handle_ibs()
266 xenoprof_log_event(v, regs, val, mode, 0); in handle_ibs()
268 ibs_log_event(val, regs, mode); in handle_ibs()
271 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); in handle_ibs()
272 ibs_log_event(val, regs, mode); in handle_ibs()
285 rdmsrl(MSR_AMD64_IBSOPRIP, val); in handle_ibs()
287 xenoprof_log_event(v, regs, val, mode, 0); in handle_ibs()
289 ibs_log_event(val, regs, mode); in handle_ibs()
291 rdmsrl(MSR_AMD64_IBSOPDATA, val); in handle_ibs()
292 ibs_log_event(val, regs, mode); in handle_ibs()
293 rdmsrl(MSR_AMD64_IBSOPDATA2, val); in handle_ibs()
294 ibs_log_event(val, regs, mode); in handle_ibs()
295 rdmsrl(MSR_AMD64_IBSOPDATA3, val); in handle_ibs()
296 ibs_log_event(val, regs, mode); in handle_ibs()
297 rdmsrl(MSR_AMD64_IBSDCLINAD, val); in handle_ibs()
298 ibs_log_event(val, regs, mode); in handle_ibs()
299 rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); in handle_ibs()
300 ibs_log_event(val, regs, mode); in handle_ibs()
350 u64 val = 0; in start_ibs() local
356 val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT; in start_ibs()
357 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; in start_ibs()
358 val |= IBS_FETCH_ENABLE; in start_ibs()
359 wrmsrl(MSR_AMD64_IBSFETCHCTL, val); in start_ibs()
384 val = op_amd_randomize_ibs_op(ibs_op_ctl); in start_ibs()
385 wrmsrl(MSR_AMD64_IBSOPCTL, val); in start_ibs()