Lines Matching refs:val
43 u64 val, tom2, start, end; in get_fam10h_pci_mmconf_base() local
69 rdmsrl(address, val); in get_fam10h_pci_mmconf_base()
72 if (!(val & (1<<21))) { in get_fam10h_pci_mmconf_base()
77 rdmsrl(address, val); in get_fam10h_pci_mmconf_base()
78 tom2 = max(val & 0xffffff800000ULL, 1ULL << 32); in get_fam10h_pci_mmconf_base()
86 val = pci_conf_read32(0, bus, slot, 1, 0x80 + (i << 3)); in get_fam10h_pci_mmconf_base()
87 if (!(val & 3)) in get_fam10h_pci_mmconf_base()
90 start = (val & 0xffffff00) << 8; /* 39:16 on 31:8*/ in get_fam10h_pci_mmconf_base()
91 val = pci_conf_read32(0, bus, slot, 1, 0x84 + (i << 3)); in get_fam10h_pci_mmconf_base()
92 end = ((val & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/ in get_fam10h_pci_mmconf_base()
142 u64 val; in fam10h_check_enable_mmcfg() local
148 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, val); in fam10h_check_enable_mmcfg()
151 if (val & FAM10H_MMIO_CONF_ENABLE) { in fam10h_check_enable_mmcfg()
152 u64 base = val & MASK; in fam10h_check_enable_mmcfg()
179 val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) | in fam10h_check_enable_mmcfg()
181 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) | in fam10h_check_enable_mmcfg()
183 wrmsrl(MSR_FAM10H_MMIO_CONF_BASE, val); in fam10h_check_enable_mmcfg()