Lines Matching refs:cfg
248 struct arm_smmu_master_cfg *cfg; member
272 struct arm_smmu_master_cfg *cfg, in iommu_group_set_iommudata() argument
278 group->cfg = cfg; in iommu_group_set_iommudata()
301 #define iommu_group_get_iommudata(group) (group)->cfg
608 struct arm_smmu_master_cfg cfg; member
660 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) argument
661 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) argument
671 struct arm_smmu_cfg cfg; member
742 struct arm_smmu_master_cfg *cfg = NULL; in find_smmu_master_cfg() local
746 cfg = iommu_group_get_iommudata(group); in find_smmu_master_cfg()
750 return cfg; in find_smmu_master_cfg()
805 master->cfg.num_streamids = masterspec->args_count; in register_smmu_master()
810 for (i = 0; i < master->cfg.num_streamids; ++i) { in register_smmu_master()
820 master->cfg.streamids[i] = streamid; in register_smmu_master()
881 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_tlb_inv_context() local
884 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_tlb_inv_context()
887 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); in arm_smmu_tlb_inv_context()
888 writel_relaxed(ARM_SMMU_CB_ASID(cfg), in arm_smmu_tlb_inv_context()
892 writel_relaxed(ARM_SMMU_CB_VMID(cfg), in arm_smmu_tlb_inv_context()
906 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_context_fault() local
910 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); in arm_smmu_context_fault()
937 iova, fsynr, cfg->cbndx); in arm_smmu_context_fault()
1021 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_init_context_bank() local
1028 stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; in arm_smmu_init_context_bank()
1029 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); in arm_smmu_init_context_bank()
1032 reg = cfg->cbar; in arm_smmu_init_context_bank()
1034 reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT; in arm_smmu_init_context_bank()
1044 reg |= ARM_SMMU_CB_VMID(cfg) << CBAR_VMID_SHIFT; in arm_smmu_init_context_bank()
1046 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx)); in arm_smmu_init_context_bank()
1056 gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx)); in arm_smmu_init_context_bank()
1109 ASSERT(smmu_domain->cfg.domain != NULL); in arm_smmu_init_context_bank()
1110 p2maddr = page_to_maddr(smmu_domain->cfg.domain->arch.p2m.root); in arm_smmu_init_context_bank()
1113 smmu_domain->cfg.domain->domain_id, p2maddr); in arm_smmu_init_context_bank()
1119 reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; in arm_smmu_init_context_bank()
1199 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_init_domain_context() local
1230 cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; in arm_smmu_init_domain_context()
1239 cfg->cbar = CBAR_TYPE_S2_TRANS; in arm_smmu_init_domain_context()
1252 cfg->cbndx = ret; in arm_smmu_init_domain_context()
1254 cfg->irptndx = atomic_inc_return(&smmu->irptndx); in arm_smmu_init_domain_context()
1255 cfg->irptndx %= smmu->num_context_irqs; in arm_smmu_init_domain_context()
1257 cfg->irptndx = cfg->cbndx; in arm_smmu_init_domain_context()
1264 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; in arm_smmu_init_domain_context()
1269 cfg->irptndx, irq); in arm_smmu_init_domain_context()
1270 cfg->irptndx = INVALID_IRPTNDX; in arm_smmu_init_domain_context()
1284 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in arm_smmu_destroy_domain_context() local
1292 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); in arm_smmu_destroy_domain_context()
1296 if (cfg->irptndx != INVALID_IRPTNDX) { in arm_smmu_destroy_domain_context()
1297 irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx]; in arm_smmu_destroy_domain_context()
1301 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_destroy_domain_context()
1367 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1368 pgd_t *pgd, *pgd_base = cfg->pgd;
1400 struct arm_smmu_master_cfg *cfg) in arm_smmu_master_configure_smrs() argument
1409 if (cfg->smrs) in arm_smmu_master_configure_smrs()
1412 smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL); in arm_smmu_master_configure_smrs()
1415 cfg->num_streamids); in arm_smmu_master_configure_smrs()
1420 for (i = 0; i < cfg->num_streamids; ++i) { in arm_smmu_master_configure_smrs()
1431 .id = cfg->streamids[i], in arm_smmu_master_configure_smrs()
1436 for (i = 0; i < cfg->num_streamids; ++i) { in arm_smmu_master_configure_smrs()
1442 cfg->smrs = smrs; in arm_smmu_master_configure_smrs()
1453 struct arm_smmu_master_cfg *cfg) in arm_smmu_master_free_smrs() argument
1457 struct arm_smmu_smr *smrs = cfg->smrs; in arm_smmu_master_free_smrs()
1463 for (i = 0; i < cfg->num_streamids; ++i) { in arm_smmu_master_free_smrs()
1470 cfg->smrs = NULL; in arm_smmu_master_free_smrs()
1475 struct arm_smmu_master_cfg *cfg) in arm_smmu_domain_add_master() argument
1482 ret = arm_smmu_master_configure_smrs(smmu, cfg); in arm_smmu_domain_add_master()
1486 for (i = 0; i < cfg->num_streamids; ++i) { in arm_smmu_domain_add_master()
1489 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; in arm_smmu_domain_add_master()
1491 (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT); in arm_smmu_domain_add_master()
1499 struct arm_smmu_master_cfg *cfg) in arm_smmu_domain_remove_master() argument
1506 if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs) in arm_smmu_domain_remove_master()
1514 for (i = 0; i < cfg->num_streamids; ++i) { in arm_smmu_domain_remove_master()
1515 u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i]; in arm_smmu_domain_remove_master()
1521 arm_smmu_master_free_smrs(smmu, cfg); in arm_smmu_domain_remove_master()
1529 struct arm_smmu_master_cfg *cfg; in arm_smmu_attach_dev() local
1564 cfg = find_smmu_master_cfg(dev); in arm_smmu_attach_dev()
1565 if (!cfg) in arm_smmu_attach_dev()
1568 ret = arm_smmu_domain_add_master(smmu_domain, cfg); in arm_smmu_attach_dev()
1578 struct arm_smmu_master_cfg *cfg; in arm_smmu_detach_dev() local
1580 cfg = find_smmu_master_cfg(dev); in arm_smmu_detach_dev()
1581 if (!cfg) in arm_smmu_detach_dev()
1585 arm_smmu_domain_remove_master(smmu_domain, cfg); in arm_smmu_detach_dev()
1779 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1780 pgd_t *pgd = cfg->pgd;
1783 if (cfg->cbar == CBAR_TYPE_S2_TRANS) {
1856 struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1858 pgdp = cfg->pgd;
1916 struct arm_smmu_master_cfg *cfg; in arm_smmu_add_device() local
1934 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL); in arm_smmu_add_device()
1935 if (!cfg) { in arm_smmu_add_device()
1940 cfg->num_streamids = 1; in arm_smmu_add_device()
1946 &cfg->streamids[0]); in arm_smmu_add_device()
1957 cfg = &master->cfg; in arm_smmu_add_device()
1960 iommu_group_set_iommudata(group, cfg, releasefn); in arm_smmu_add_device()
2535 struct iommu_domain *cfg; in arm_smmu_iotlb_flush_all() local
2538 list_for_each_entry(cfg, &smmu_domain->contexts, list) { in arm_smmu_iotlb_flush_all()
2544 if (unlikely(!ACCESS_ONCE(cfg->priv->smmu))) in arm_smmu_iotlb_flush_all()
2546 arm_smmu_tlb_inv_context(cfg->priv); in arm_smmu_iotlb_flush_all()
2636 domain->priv->cfg.domain = d; in arm_smmu_assign_dev()
2664 if (!domain || domain->priv->cfg.domain != d) { in arm_smmu_deassign_dev()