Lines Matching refs:u32
149 u32 mfg_id;
205 u32 enterprise_id;
246 u32 info_offset;
247 u32 info_count;
425 u32 reserved;
427 u32 proximity_domain;
442 u32 id; /* Hardware ID of event timer block */
569 u32 node_count;
570 u32 node_offset;
571 u32 reserved;
581 u32 reserved;
582 u32 mapping_count;
583 u32 mapping_offset;
598 u32 input_base; /* Lowest value in input range */
599 u32 id_count; /* Number of IDs */
600 u32 output_base; /* Lowest value in output range */
601 u32 output_reference; /* A reference to the output node */
602 u32 flags;
610 u32 cache_coherency;
637 u32 its_count;
638 u32 identifiers[1]; /* GIC ITS identifier arrary */
642 u32 node_flags;
650 u32 ats_attribute;
651 u32 pci_segment_number;
662 u32 model;
663 u32 flags;
664 u32 global_interrupt_offset;
665 u32 context_interrupt_count;
666 u32 context_interrupt_offset;
667 u32 pmu_interrupt_count;
668 u32 pmu_interrupt_offset;
686 u32 flags;
687 u32 reserved;
689 u32 model; /* O: generic SMMUv3 */
690 u32 event_gsiv;
691 u32 pri_gsiv;
692 u32 gerr_gsiv;
693 u32 sync_gsiv;
713 u32 info; /* Common virtualization info */
770 u32 iommu_attr;
846 u32 extended_data;
898 u32 reserved;
919 u32 global_interrupt;
946 u32 type;
947 u32 length;
969 u32 algorithm;
971 u32 bit_length;
972 u32 exponent;
980 u32 version;
984 u32 slic_version;
1006 u32 interrupt;
1018 u32 pci_flags;
1020 u32 reserved2;
1047 u32 interrupt;
1080 u32 max_log_length; /* Maximum length for the event log area */
1111 u32 flags;
1131 u32 header_length; /* Watchdog Header Length */
1137 u32 timer_period; /* Period of one timer count (msec) */
1138 u32 max_count; /* Maximum counter value supported */
1139 u32 min_count; /* Minimum counter value */
1142 u32 entries; /* Number of watchdog entries that follow */
1157 u32 value; /* Value used with Read/Write register */
1158 u32 mask; /* Bitmask required for this register instruction */