Lines Matching refs:c1
66 #define FPSCR p10,7,c1,c0,0 /* Floating-Point Status and Control Register */
76 #define DBGDSCRINT p14,0,c0,c1,0 /* Debug Status and Control Internal */
83 #define DBGBVR1 p14,0,c0,c1,4 /* Breakpoint Value 1 */
84 #define DBGBCR1 p14,0,c0,c1,5 /* Breakpoint Control 1 */
85 #define DBGOSLAR p14,0,c1,c0,4 /* OS Lock Access */
86 #define DBGOSLSR p14,0,c1,c1,4 /* OS Lock Status Register */
87 #define DBGOSDLR p14,0,c1,c3,4 /* OS Double Lock */
88 #define DBGPRCR p14,0,c1,c4,4 /* Debug Power Control Register */
94 #define DBGDRAR64 p14,0,c1 /* Debug ROM Address Register (64-bit access) */
95 #define DBGDRAR p14,0,c1,c0,0 /* Debug ROM Address Register (32-bit access) */
96 #define TEEHBR p14,6,c1,c0,0 /* ThumbEE Handler Base Register */
97 #define JOSCR p14,7,c1,c0,0 /* Jazelle OS Control Register */
110 #define ID_PFR0 p15,0,c0,c1,0 /* Processor Feature Register 0 */
111 #define ID_PFR1 p15,0,c0,c1,1 /* Processor Feature Register 1 */
112 #define ID_DFR0 p15,0,c0,c1,2 /* Debug Feature Register 0 */
113 #define ID_AFR0 p15,0,c0,c1,3 /* Auxiliary Feature Register 0 */
114 #define ID_MMFR0 p15,0,c0,c1,4 /* Memory Model Feature Register 0 */
115 #define ID_MMFR1 p15,0,c0,c1,5 /* Memory Model Feature Register 1 */
116 #define ID_MMFR2 p15,0,c0,c1,6 /* Memory Model Feature Register 2 */
117 #define ID_MMFR3 p15,0,c0,c1,7 /* Memory Model Feature Register 3 */
131 #define SCTLR p15,0,c1,c0,0 /* System Control Register */
132 #define ACTLR p15,0,c1,c0,1 /* Auxiliary Control Register */
133 #define CPACR p15,0,c1,c0,2 /* Coprocessor Access Control Register */
134 #define SCR p15,0,c1,c1,0 /* Secure Configuration Register */
135 #define NSACR p15,0,c1,c1,2 /* Non-Secure Access Control Register */
136 #define HSCTLR p15,4,c1,c0,0 /* Hyp. System Control Register */
137 #define HCR p15,4,c1,c1,0 /* Hyp. Configuration Register */
138 #define HDCR p15,4,c1,c1,1 /* Hyp. Debug Configuration Register */
139 #define HCPTR p15,4,c1,c1,2 /* Hyp. Coprocessor Trap Register */
140 #define HSTR p15,4,c1,c1,3 /* Hyp. System Trap Register */
150 #define VTCR p15,4,c2,c1,2 /* Virtualization Translation Control Register */
161 #define ADFSR p15,0,c5,c1,0 /* Auxiliary Data Fault Status Register */
162 #define AIFSR p15,0,c5,c1,1 /* Auxiliary Instruction Fault Status Register */
175 #define ICIALLUIS p15,0,c7,c1,0 /* Invalidate all instruction caches to PoU inner shareable…
176 #define BPIALLIS p15,0,c7,c1,6 /* Invalidate entire branch predictor array inner shareable…
266 #define CNTKCTL p15,0,c14,c1,0 /* Time counter kernel control */
273 #define CNTHCTL p15,4,c14,c1,0 /* Time counter hyp. control */