Lines Matching refs:c2
77 #define DBGDSCREXT p14,0,c0,c2,2 /* Debug Status and Control External */
100 #define DBGDSAR64 p14,0,c2 /* Debug Self Address Offset Register (64-bit access) */
101 #define DBGDSAR p14,0,c2,c0,0 /* Debug Self Address Offset Register (32-bit access) */
102 #define JMCR p14,7,c2,c0,0 /* Jazelle Main Configuration Register */
118 #define ID_ISAR0 p15,0,c0,c2,0 /* ISA Feature Register 0 */
119 #define ID_ISAR1 p15,0,c0,c2,1 /* ISA Feature Register 1 */
120 #define ID_ISAR2 p15,0,c0,c2,2 /* ISA Feature Register 2 */
121 #define ID_ISAR3 p15,0,c0,c2,3 /* ISA Feature Register 3 */
122 #define ID_ISAR4 p15,0,c0,c2,4 /* ISA Feature Register 4 */
123 #define ID_ISAR5 p15,0,c0,c2,5 /* ISA Feature Register 5 */
143 #define TTBCR p15,0,c2,c0,2 /* Translatation Table Base Control Register */
144 #define TTBR0 p15,0,c2 /* Translation Table Base Reg. 0 */
145 #define TTBR1 p15,1,c2 /* Translation Table Base Reg. 1 */
146 #define HTTBR p15,4,c2 /* Hyp. Translation Table Base Register */
147 #define TTBR0_32 p15,0,c2,c0,0 /* 32-bit access to TTBR0 */
148 #define TTBR1_32 p15,0,c2,c0,1 /* 32-bit access to TTBR1 */
149 #define HTCR p15,4,c2,c0,2 /* Hyp. Translation Control Register */
150 #define VTCR p15,4,c2,c1,2 /* Virtualization Translation Control Register */
151 #define VTTBR p15,6,c2 /* Virtualization Translation Table Base Register */
163 #define HSR p15,4,c5,c2,0 /* Hyp. Syndrome Register */
239 #define MAIR0 p15,0,c10,c2,0 /* Memory Attribute Indirection Register 0 AKA PRRR */
240 #define MAIR1 p15,0,c10,c2,1 /* Memory Attribute Indirection Register 1 AKA NMRR */
241 #define HMAIR0 p15,4,c10,c2,0 /* Hyp. Memory Attribute Indirection Register 0 */
242 #define HMAIR1 p15,4,c10,c2,1 /* Hyp. Memory Attribute Indirection Register 1 */
267 #define CNTP_TVAL p15,0,c14,c2,0 /* Physical Timer value */
268 #define CNTP_CTL p15,0,c14,c2,1 /* Physical Timer control register */
274 #define CNTHP_TVAL p15,4,c14,c2,0 /* Hyp. Timer value */
275 #define CNTHP_CTL p15,4,c14,c2,1 /* Hyp. Timer control register */