Lines Matching refs:_AC
57 #define MPIDR_UP (_AC(1,U) << _MPIDR_UP)
59 #define MPIDR_SMP (_AC(1,U) << _MPIDR_SMP)
61 #define MPIDR_AFF0_MASK (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
63 #define MPIDR_HWID_MASK _AC(0xff00ffffff,UL)
65 #define MPIDR_HWID_MASK _AC(0xffffff,U)
84 #define AFFINITY_MASK(level) ~((_AC(0x1,UL) << MPIDR_LEVEL_SHIFT(level)) - 1)
87 #define TTBCR_EAE _AC(0x80000000,U)
88 #define TTBCR_N_MASK _AC(0x07,U)
89 #define TTBCR_N_16KB _AC(0x00,U)
90 #define TTBCR_N_8KB _AC(0x01,U)
91 #define TTBCR_N_4KB _AC(0x02,U)
92 #define TTBCR_N_2KB _AC(0x03,U)
93 #define TTBCR_N_1KB _AC(0x04,U)
99 #define TTBCR_PD0 (_AC(1,U)<<4)
100 #define TTBCR_PD1 (_AC(1,U)<<5)
104 #define SCTLR_TE (_AC(1,U)<<30)
105 #define SCTLR_AFE (_AC(1,U)<<29)
106 #define SCTLR_TRE (_AC(1,U)<<28)
107 #define SCTLR_NMFI (_AC(1,U)<<27)
108 #define SCTLR_EE (_AC(1,U)<<25)
109 #define SCTLR_VE (_AC(1,U)<<24)
110 #define SCTLR_U (_AC(1,U)<<22)
111 #define SCTLR_FI (_AC(1,U)<<21)
112 #define SCTLR_WXN (_AC(1,U)<<19)
113 #define SCTLR_HA (_AC(1,U)<<17)
114 #define SCTLR_RR (_AC(1,U)<<14)
115 #define SCTLR_V (_AC(1,U)<<13)
116 #define SCTLR_I (_AC(1,U)<<12)
117 #define SCTLR_Z (_AC(1,U)<<11)
118 #define SCTLR_SW (_AC(1,U)<<10)
119 #define SCTLR_B (_AC(1,U)<<7)
120 #define SCTLR_C (_AC(1,U)<<2)
121 #define SCTLR_A (_AC(1,U)<<1)
122 #define SCTLR_M (_AC(1,U)<<0)
124 #define HSCTLR_BASE _AC(0x30c51878,U)
127 #define HCR_RW (_AC(1,UL)<<31) /* Register Width, ARM64 only */
128 #define HCR_TGE (_AC(1,UL)<<27) /* Trap General Exceptions */
129 #define HCR_TVM (_AC(1,UL)<<26) /* Trap Virtual Memory Controls */
130 #define HCR_TTLB (_AC(1,UL)<<25) /* Trap TLB Maintenance Operations */
131 #define HCR_TPU (_AC(1,UL)<<24) /* Trap Cache Maintenance Operations to PoU */
132 #define HCR_TPC (_AC(1,UL)<<23) /* Trap Cache Maintenance Operations to PoC */
133 #define HCR_TSW (_AC(1,UL)<<22) /* Trap Set/Way Cache Maintenance Operations */
134 #define HCR_TAC (_AC(1,UL)<<21) /* Trap ACTLR Accesses */
135 #define HCR_TIDCP (_AC(1,UL)<<20) /* Trap lockdown */
136 #define HCR_TSC (_AC(1,UL)<<19) /* Trap SMC instruction */
137 #define HCR_TID3 (_AC(1,UL)<<18) /* Trap ID Register Group 3 */
138 #define HCR_TID2 (_AC(1,UL)<<17) /* Trap ID Register Group 2 */
139 #define HCR_TID1 (_AC(1,UL)<<16) /* Trap ID Register Group 1 */
140 #define HCR_TID0 (_AC(1,UL)<<15) /* Trap ID Register Group 0 */
141 #define HCR_TWE (_AC(1,UL)<<14) /* Trap WFE instruction */
142 #define HCR_TWI (_AC(1,UL)<<13) /* Trap WFI instruction */
143 #define HCR_DC (_AC(1,UL)<<12) /* Default cacheable */
144 #define HCR_BSU_MASK (_AC(3,UL)<<10) /* Barrier Shareability Upgrade */
145 #define HCR_BSU_NONE (_AC(0,UL)<<10)
146 #define HCR_BSU_INNER (_AC(1,UL)<<10)
147 #define HCR_BSU_OUTER (_AC(2,UL)<<10)
148 #define HCR_BSU_FULL (_AC(3,UL)<<10)
149 #define HCR_FB (_AC(1,UL)<<9) /* Force Broadcast of Cache/BP/TLB operations */
150 #define HCR_VA (_AC(1,UL)<<8) /* Virtual Asynchronous Abort */
151 #define HCR_VI (_AC(1,UL)<<7) /* Virtual IRQ */
152 #define HCR_VF (_AC(1,UL)<<6) /* Virtual FIQ */
153 #define HCR_AMO (_AC(1,UL)<<5) /* Override CPSR.A */
154 #define HCR_IMO (_AC(1,UL)<<4) /* Override CPSR.I */
155 #define HCR_FMO (_AC(1,UL)<<3) /* Override CPSR.F */
156 #define HCR_PTW (_AC(1,UL)<<2) /* Protected Walk */
157 #define HCR_SWIO (_AC(1,UL)<<1) /* Set/Way Invalidation Override */
158 #define HCR_VM (_AC(1,UL)<<0) /* Virtual MMU Enable */
172 #define TCR_SZ_MASK (_AC(0x3f,UL))
174 #define TCR_EPD0 (_AC(0x1,UL)<<7)
175 #define TCR_EPD1 (_AC(0x1,UL)<<23)
177 #define TCR_IRGN0_NC (_AC(0x0,UL)<<8)
178 #define TCR_IRGN0_WBWA (_AC(0x1,UL)<<8)
179 #define TCR_IRGN0_WT (_AC(0x2,UL)<<8)
180 #define TCR_IRGN0_WB (_AC(0x3,UL)<<8)
182 #define TCR_ORGN0_NC (_AC(0x0,UL)<<10)
183 #define TCR_ORGN0_WBWA (_AC(0x1,UL)<<10)
184 #define TCR_ORGN0_WT (_AC(0x2,UL)<<10)
185 #define TCR_ORGN0_WB (_AC(0x3,UL)<<10)
187 #define TCR_SH0_NS (_AC(0x0,UL)<<12)
188 #define TCR_SH0_OS (_AC(0x2,UL)<<12)
189 #define TCR_SH0_IS (_AC(0x3,UL)<<12)
193 #define TCR_TG0_MASK (_AC(0x3,UL)<<TCR_TG0_SHIFT)
194 #define TCR_TG0_4K (_AC(0x0,UL)<<TCR_TG0_SHIFT)
195 #define TCR_TG0_64K (_AC(0x1,UL)<<TCR_TG0_SHIFT)
196 #define TCR_TG0_16K (_AC(0x2,UL)<<TCR_TG0_SHIFT)
200 #define TCR_EL1_TG1_MASK (_AC(0x3,UL)<<TCR_EL1_TG1_SHIFT)
201 #define TCR_EL1_TG1_16K (_AC(0x1,UL)<<TCR_EL1_TG1_SHIFT)
202 #define TCR_EL1_TG1_4K (_AC(0x2,UL)<<TCR_EL1_TG1_SHIFT)
203 #define TCR_EL1_TG1_64K (_AC(0x3,UL)<<TCR_EL1_TG1_SHIFT)
210 #define TCR_EL1_IPS_MASK (_AC(0x7,ULL)<<TCR_EL1_IPS_SHIFT)
211 #define TCR_EL1_IPS_32_BIT (_AC(0x0,ULL)<<TCR_EL1_IPS_SHIFT)
212 #define TCR_EL1_IPS_36_BIT (_AC(0x1,ULL)<<TCR_EL1_IPS_SHIFT)
213 #define TCR_EL1_IPS_40_BIT (_AC(0x2,ULL)<<TCR_EL1_IPS_SHIFT)
214 #define TCR_EL1_IPS_42_BIT (_AC(0x3,ULL)<<TCR_EL1_IPS_SHIFT)
215 #define TCR_EL1_IPS_44_BIT (_AC(0x4,ULL)<<TCR_EL1_IPS_SHIFT)
216 #define TCR_EL1_IPS_48_BIT (_AC(0x5,ULL)<<TCR_EL1_IPS_SHIFT)
217 #define TCR_EL1_IPS_52_BIT (_AC(0x6,ULL)<<TCR_EL1_IPS_SHIFT)
233 #define TCR_EL1_TBI0 (_AC(0x1,ULL)<<37)
234 #define TCR_EL1_TBI1 (_AC(0x1,ULL)<<38)
239 #define TCR_TBI (_AC(0x1,UL)<<20)
241 #define TCR_RES1 (_AC(1,UL)<<31|_AC(1,UL)<<23)
245 #define TCR_RES1 (_AC(1,UL)<<31)
255 #define VTCR_IRGN0_NC (_AC(0x0,UL)<<8)
256 #define VTCR_IRGN0_WBWA (_AC(0x1,UL)<<8)
257 #define VTCR_IRGN0_WT (_AC(0x2,UL)<<8)
258 #define VTCR_IRGN0_WB (_AC(0x3,UL)<<8)
260 #define VTCR_ORGN0_NC (_AC(0x0,UL)<<10)
261 #define VTCR_ORGN0_WBWA (_AC(0x1,UL)<<10)
262 #define VTCR_ORGN0_WT (_AC(0x2,UL)<<10)
263 #define VTCR_ORGN0_WB (_AC(0x3,UL)<<10)
265 #define VTCR_SH0_NS (_AC(0x0,UL)<<12)
266 #define VTCR_SH0_OS (_AC(0x2,UL)<<12)
267 #define VTCR_SH0_IS (_AC(0x3,UL)<<12)
271 #define VTCR_TG0_4K (_AC(0x0,UL)<<14)
272 #define VTCR_TG0_64K (_AC(0x1,UL)<<14)
273 #define VTCR_TG0_16K (_AC(0x2,UL)<<14)
277 #define VTCR_VS (_AC(0x1,UL)<<19)
281 #define VTCR_RES1 (_AC(1,UL)<<31)
284 #define HCPTR_TTA ((_AC(1,U)<<20)) /* Trap trace registers */
285 #define HCPTR_CP(x) ((_AC(1,U)<<(x))) /* Trap Coprocessor x */
286 #define HCPTR_CP_MASK ((_AC(1,U)<<14)-1)
289 #define HSTR_T(x) ((_AC(1,U)<<(x))) /* Trap Cp15 c<x> */
292 #define HDCR_TDRA (_AC(1,U)<<11) /* Trap Debug ROM access */
293 #define HDCR_TDOSA (_AC(1,U)<<10) /* Trap Debug-OS-related register access */
294 #define HDCR_TDA (_AC(1,U)<<9) /* Trap Debug Access */
295 #define HDCR_TDE (_AC(1,U)<<8) /* Route Soft Debug exceptions from EL1/EL1 to EL2 …
296 #define HDCR_TPM (_AC(1,U)<<6) /* Trap Performance Monitors accesses */
297 #define HDCR_TPMCR (_AC(1,U)<<5) /* Trap PMCR accesses */
328 #define FSR_LPAE (_AC(1,UL)<<9)
330 #define FSRS_FS_DEBUG (_AC(0,UL)<<10|_AC(0x2,UL)<<0)
332 #define FSRL_STATUS_DEBUG (_AC(0x22,UL)<<0)
680 #define PAR_F (_AC(1,U)<<0)
684 #define PAR_FSC_MASK (_AC(0x3f,U)<<PAR_FSC_SHIFT)
685 #define PAR_STAGE21 (_AC(1,U)<<8) /* Stage 2 Fault During Stage 1 Walk */
686 #define PAR_STAGE2 (_AC(1,U)<<9) /* Stage 2 Fault */
691 #define PAR_NS (_AC(1,U)<<9) /* Non-Secure */
693 #define PAR_SH_MASK (_AC(3,U)<<PAR_SH_SHIFT)
706 #define FSC_TYPE_MASK (_AC(0x3,U)<<4)
707 #define FSC_TYPE_FAULT (_AC(0x00,U)<<4)
708 #define FSC_TYPE_ABT (_AC(0x01,U)<<4)
709 #define FSC_TYPE_OTH (_AC(0x02,U)<<4)
710 #define FSC_TYPE_IMPL (_AC(0x03,U)<<4)
725 #define FSC_LL_MASK (_AC(0x03,U)<<0)