1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/completion.h>
10 #include <linux/cpuidle.h>
11 #include <linux/debugfs.h>
12 #include <linux/device.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/kthread.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/nvmem-consumer.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_domain.h>
25 #include <linux/pm_opp.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/reset.h>
29 #include <linux/seq_file.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/thermal.h>
33
34 /* svs bank 1-line software id */
35 #define SVSB_CPU_LITTLE BIT(0)
36 #define SVSB_CPU_BIG BIT(1)
37 #define SVSB_CCI BIT(2)
38 #define SVSB_GPU BIT(3)
39
40 /* svs bank 2-line type */
41 #define SVSB_LOW BIT(8)
42 #define SVSB_HIGH BIT(9)
43
44 /* svs bank mode support */
45 #define SVSB_MODE_ALL_DISABLE 0
46 #define SVSB_MODE_INIT01 BIT(1)
47 #define SVSB_MODE_INIT02 BIT(2)
48 #define SVSB_MODE_MON BIT(3)
49
50 /* svs bank volt flags */
51 #define SVSB_INIT01_PD_REQ BIT(0)
52 #define SVSB_INIT01_VOLT_IGNORE BIT(1)
53 #define SVSB_INIT01_VOLT_INC_ONLY BIT(2)
54 #define SVSB_MON_VOLT_IGNORE BIT(16)
55 #define SVSB_REMOVE_DVTFIXED_VOLT BIT(24)
56
57 /* svs bank register fields and common configuration */
58 #define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0)
59 #define SVSB_DET_MAX FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff)
60 #define SVSB_DET_WINDOW 0xa28
61
62 /* DESCHAR */
63 #define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0)
64 #define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8)
65
66 /* TEMPCHAR */
67 #define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0)
68 #define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8)
69 #define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16)
70
71 /* DETCHAR */
72 #define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0)
73 #define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8)
74
75 /* SVSEN (PTPEN) */
76 #define SVSB_PTPEN_INIT01 BIT(0)
77 #define SVSB_PTPEN_MON BIT(1)
78 #define SVSB_PTPEN_INIT02 (SVSB_PTPEN_INIT01 | BIT(2))
79 #define SVSB_PTPEN_OFF 0x0
80
81 /* FREQPCTS */
82 #define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0)
83 #define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8)
84 #define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16)
85 #define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24)
86
87 /* INTSTS */
88 #define SVSB_INTSTS_VAL_CLEAN 0x00ffffff
89 #define SVSB_INTSTS_F0_COMPLETE BIT(0)
90 #define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16)
91 #define SVSB_RUNCONFIG_DEFAULT 0x80000000
92
93 /* LIMITVALS */
94 #define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0)
95 #define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8)
96 #define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16)
97 #define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24)
98 #define SVSB_VAL_DTHI 0x1
99 #define SVSB_VAL_DTLO 0xfe
100
101 /* INTEN */
102 #define SVSB_INTEN_F0EN BIT(0)
103 #define SVSB_INTEN_DACK0UPEN BIT(8)
104 #define SVSB_INTEN_DC0EN BIT(9)
105 #define SVSB_INTEN_DC1EN BIT(10)
106 #define SVSB_INTEN_DACK0LOEN BIT(11)
107 #define SVSB_INTEN_INITPROD_OVF_EN BIT(12)
108 #define SVSB_INTEN_INITSUM_OVF_EN BIT(14)
109 #define SVSB_INTEN_MONVOPEN GENMASK(23, 16)
110 #define SVSB_INTEN_INIT0x (SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN | \
111 SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN | \
112 SVSB_INTEN_DACK0LOEN | \
113 SVSB_INTEN_INITPROD_OVF_EN | \
114 SVSB_INTEN_INITSUM_OVF_EN)
115
116 /* TSCALCS */
117 #define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0)
118 #define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12)
119
120 /* INIT2VALS */
121 #define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0)
122 #define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16)
123
124 /* VOPS */
125 #define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0)
126 #define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8)
127 #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16)
128 #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24)
129
130 /* svs bank related setting */
131 #define BITS8 8
132 #define MAX_OPP_ENTRIES 16
133 #define REG_BYTES 4
134 #define SVSB_DC_SIGNED_BIT BIT(15)
135 #define SVSB_DET_CLK_EN BIT(31)
136 #define SVSB_TEMP_LOWER_BOUND 0xb2
137 #define SVSB_TEMP_UPPER_BOUND 0x64
138
139 static DEFINE_SPINLOCK(svs_lock);
140
141 #ifdef CONFIG_DEBUG_FS
142 #define debug_fops_ro(name) \
143 static int svs_##name##_debug_open(struct inode *inode, \
144 struct file *filp) \
145 { \
146 return single_open(filp, svs_##name##_debug_show, \
147 inode->i_private); \
148 } \
149 static const struct file_operations svs_##name##_debug_fops = { \
150 .owner = THIS_MODULE, \
151 .open = svs_##name##_debug_open, \
152 .read = seq_read, \
153 .llseek = seq_lseek, \
154 .release = single_release, \
155 }
156
157 #define debug_fops_rw(name) \
158 static int svs_##name##_debug_open(struct inode *inode, \
159 struct file *filp) \
160 { \
161 return single_open(filp, svs_##name##_debug_show, \
162 inode->i_private); \
163 } \
164 static const struct file_operations svs_##name##_debug_fops = { \
165 .owner = THIS_MODULE, \
166 .open = svs_##name##_debug_open, \
167 .read = seq_read, \
168 .write = svs_##name##_debug_write, \
169 .llseek = seq_lseek, \
170 .release = single_release, \
171 }
172
173 #define svs_dentry_data(name) {__stringify(name), &svs_##name##_debug_fops}
174 #endif
175
176 /**
177 * enum svsb_phase - svs bank phase enumeration
178 * @SVSB_PHASE_ERROR: svs bank encounters unexpected condition
179 * @SVSB_PHASE_INIT01: svs bank basic init for data calibration
180 * @SVSB_PHASE_INIT02: svs bank can provide voltages to opp table
181 * @SVSB_PHASE_MON: svs bank can provide voltages with thermal effect
182 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
183 *
184 * Each svs bank has its own independent phase and we enable each svs bank by
185 * running their phase orderly. However, when svs bank encounters unexpected
186 * condition, it will fire an irq (PHASE_ERROR) to inform svs software.
187 *
188 * svs bank general phase-enabled order:
189 * SVSB_PHASE_INIT01 -> SVSB_PHASE_INIT02 -> SVSB_PHASE_MON
190 */
191 enum svsb_phase {
192 SVSB_PHASE_ERROR = 0,
193 SVSB_PHASE_INIT01,
194 SVSB_PHASE_INIT02,
195 SVSB_PHASE_MON,
196 SVSB_PHASE_MAX,
197 };
198
199 enum svs_reg_index {
200 DESCHAR = 0,
201 TEMPCHAR,
202 DETCHAR,
203 AGECHAR,
204 DCCONFIG,
205 AGECONFIG,
206 FREQPCT30,
207 FREQPCT74,
208 LIMITVALS,
209 VBOOT,
210 DETWINDOW,
211 CONFIG,
212 TSCALCS,
213 RUNCONFIG,
214 SVSEN,
215 INIT2VALS,
216 DCVALUES,
217 AGEVALUES,
218 VOP30,
219 VOP74,
220 TEMP,
221 INTSTS,
222 INTSTSRAW,
223 INTEN,
224 CHKINT,
225 CHKSHIFT,
226 STATUS,
227 VDESIGN30,
228 VDESIGN74,
229 DVT30,
230 DVT74,
231 AGECOUNT,
232 SMSTATE0,
233 SMSTATE1,
234 CTL0,
235 DESDETSEC,
236 TEMPAGESEC,
237 CTRLSPARE0,
238 CTRLSPARE1,
239 CTRLSPARE2,
240 CTRLSPARE3,
241 CORESEL,
242 THERMINTST,
243 INTST,
244 THSTAGE0ST,
245 THSTAGE1ST,
246 THSTAGE2ST,
247 THAHBST0,
248 THAHBST1,
249 SPARE0,
250 SPARE1,
251 SPARE2,
252 SPARE3,
253 THSLPEVEB,
254 SVS_REG_MAX,
255 };
256
257 static const u32 svs_regs_v2[] = {
258 [DESCHAR] = 0xc00,
259 [TEMPCHAR] = 0xc04,
260 [DETCHAR] = 0xc08,
261 [AGECHAR] = 0xc0c,
262 [DCCONFIG] = 0xc10,
263 [AGECONFIG] = 0xc14,
264 [FREQPCT30] = 0xc18,
265 [FREQPCT74] = 0xc1c,
266 [LIMITVALS] = 0xc20,
267 [VBOOT] = 0xc24,
268 [DETWINDOW] = 0xc28,
269 [CONFIG] = 0xc2c,
270 [TSCALCS] = 0xc30,
271 [RUNCONFIG] = 0xc34,
272 [SVSEN] = 0xc38,
273 [INIT2VALS] = 0xc3c,
274 [DCVALUES] = 0xc40,
275 [AGEVALUES] = 0xc44,
276 [VOP30] = 0xc48,
277 [VOP74] = 0xc4c,
278 [TEMP] = 0xc50,
279 [INTSTS] = 0xc54,
280 [INTSTSRAW] = 0xc58,
281 [INTEN] = 0xc5c,
282 [CHKINT] = 0xc60,
283 [CHKSHIFT] = 0xc64,
284 [STATUS] = 0xc68,
285 [VDESIGN30] = 0xc6c,
286 [VDESIGN74] = 0xc70,
287 [DVT30] = 0xc74,
288 [DVT74] = 0xc78,
289 [AGECOUNT] = 0xc7c,
290 [SMSTATE0] = 0xc80,
291 [SMSTATE1] = 0xc84,
292 [CTL0] = 0xc88,
293 [DESDETSEC] = 0xce0,
294 [TEMPAGESEC] = 0xce4,
295 [CTRLSPARE0] = 0xcf0,
296 [CTRLSPARE1] = 0xcf4,
297 [CTRLSPARE2] = 0xcf8,
298 [CTRLSPARE3] = 0xcfc,
299 [CORESEL] = 0xf00,
300 [THERMINTST] = 0xf04,
301 [INTST] = 0xf08,
302 [THSTAGE0ST] = 0xf0c,
303 [THSTAGE1ST] = 0xf10,
304 [THSTAGE2ST] = 0xf14,
305 [THAHBST0] = 0xf18,
306 [THAHBST1] = 0xf1c,
307 [SPARE0] = 0xf20,
308 [SPARE1] = 0xf24,
309 [SPARE2] = 0xf28,
310 [SPARE3] = 0xf2c,
311 [THSLPEVEB] = 0xf30,
312 };
313
314 /**
315 * struct svs_platform - svs platform control
316 * @base: svs platform register base
317 * @dev: svs platform device
318 * @main_clk: main clock for svs bank
319 * @pbank: svs bank pointer needing to be protected by spin_lock section
320 * @banks: svs banks that svs platform supports
321 * @rst: svs platform reset control
322 * @efuse_max: total number of svs efuse
323 * @tefuse_max: total number of thermal efuse
324 * @regs: svs platform registers map
325 * @bank_max: total number of svs banks
326 * @efuse: svs efuse data received from NVMEM framework
327 * @tefuse: thermal efuse data received from NVMEM framework
328 */
329 struct svs_platform {
330 void __iomem *base;
331 struct device *dev;
332 struct clk *main_clk;
333 struct svs_bank *pbank;
334 struct svs_bank *banks;
335 struct reset_control *rst;
336 size_t efuse_max;
337 size_t tefuse_max;
338 const u32 *regs;
339 u32 bank_max;
340 u32 *efuse;
341 u32 *tefuse;
342 };
343
344 struct svs_platform_data {
345 char *name;
346 struct svs_bank *banks;
347 bool (*efuse_parsing)(struct svs_platform *svsp);
348 int (*probe)(struct svs_platform *svsp);
349 const u32 *regs;
350 u32 bank_max;
351 };
352
353 /**
354 * struct svs_bank - svs bank representation
355 * @dev: bank device
356 * @opp_dev: device for opp table/buck control
357 * @init_completion: the timeout completion for bank init
358 * @buck: regulator used by opp_dev
359 * @tzd: thermal zone device for getting temperature
360 * @lock: mutex lock to protect voltage update process
361 * @set_freq_pct: function pointer to set bank frequency percent table
362 * @get_volts: function pointer to get bank voltages
363 * @name: bank name
364 * @buck_name: regulator name
365 * @tzone_name: thermal zone name
366 * @phase: bank current phase
367 * @volt_od: bank voltage overdrive
368 * @reg_data: bank register data in different phase for debug purpose
369 * @pm_runtime_enabled_count: bank pm runtime enabled count
370 * @mode_support: bank mode support.
371 * @freq_base: reference frequency for bank init
372 * @turn_freq_base: refenrece frequency for 2-line turn point
373 * @vboot: voltage request for bank init01 only
374 * @opp_dfreq: default opp frequency table
375 * @opp_dvolt: default opp voltage table
376 * @freq_pct: frequency percent table for bank init
377 * @volt: bank voltage table
378 * @volt_step: bank voltage step
379 * @volt_base: bank voltage base
380 * @volt_flags: bank voltage flags
381 * @vmax: bank voltage maximum
382 * @vmin: bank voltage minimum
383 * @age_config: bank age configuration
384 * @age_voffset_in: bank age voltage offset
385 * @dc_config: bank dc configuration
386 * @dc_voffset_in: bank dc voltage offset
387 * @dvt_fixed: bank dvt fixed value
388 * @vco: bank VCO value
389 * @chk_shift: bank chicken shift
390 * @core_sel: bank selection
391 * @opp_count: bank opp count
392 * @int_st: bank interrupt identification
393 * @sw_id: bank software identification
394 * @cpu_id: cpu core id for SVS CPU bank use only
395 * @ctl0: TS-x selection
396 * @temp: bank temperature
397 * @tzone_htemp: thermal zone high temperature threshold
398 * @tzone_htemp_voffset: thermal zone high temperature voltage offset
399 * @tzone_ltemp: thermal zone low temperature threshold
400 * @tzone_ltemp_voffset: thermal zone low temperature voltage offset
401 * @bts: svs efuse data
402 * @mts: svs efuse data
403 * @bdes: svs efuse data
404 * @mdes: svs efuse data
405 * @mtdes: svs efuse data
406 * @dcbdet: svs efuse data
407 * @dcmdet: svs efuse data
408 * @turn_pt: 2-line turn point tells which opp_volt calculated by high/low bank
409 * @type: bank type to represent it is 2-line (high/low) bank or 1-line bank
410 *
411 * Svs bank will generate suitalbe voltages by below general math equation
412 * and provide these voltages to opp voltage table.
413 *
414 * opp_volt[i] = (volt[i] * volt_step) + volt_base;
415 */
416 struct svs_bank {
417 struct device *dev;
418 struct device *opp_dev;
419 struct completion init_completion;
420 struct regulator *buck;
421 struct thermal_zone_device *tzd;
422 struct mutex lock; /* lock to protect voltage update process */
423 void (*set_freq_pct)(struct svs_platform *svsp);
424 void (*get_volts)(struct svs_platform *svsp);
425 char *name;
426 char *buck_name;
427 char *tzone_name;
428 enum svsb_phase phase;
429 s32 volt_od;
430 u32 reg_data[SVSB_PHASE_MAX][SVS_REG_MAX];
431 u32 pm_runtime_enabled_count;
432 u32 mode_support;
433 u32 freq_base;
434 u32 turn_freq_base;
435 u32 vboot;
436 u32 opp_dfreq[MAX_OPP_ENTRIES];
437 u32 opp_dvolt[MAX_OPP_ENTRIES];
438 u32 freq_pct[MAX_OPP_ENTRIES];
439 u32 volt[MAX_OPP_ENTRIES];
440 u32 volt_step;
441 u32 volt_base;
442 u32 volt_flags;
443 u32 vmax;
444 u32 vmin;
445 u32 age_config;
446 u32 age_voffset_in;
447 u32 dc_config;
448 u32 dc_voffset_in;
449 u32 dvt_fixed;
450 u32 vco;
451 u32 chk_shift;
452 u32 core_sel;
453 u32 opp_count;
454 u32 int_st;
455 u32 sw_id;
456 u32 cpu_id;
457 u32 ctl0;
458 u32 temp;
459 u32 tzone_htemp;
460 u32 tzone_htemp_voffset;
461 u32 tzone_ltemp;
462 u32 tzone_ltemp_voffset;
463 u32 bts;
464 u32 mts;
465 u32 bdes;
466 u32 mdes;
467 u32 mtdes;
468 u32 dcbdet;
469 u32 dcmdet;
470 u32 turn_pt;
471 u32 type;
472 };
473
percent(u32 numerator,u32 denominator)474 static u32 percent(u32 numerator, u32 denominator)
475 {
476 /* If not divide 1000, "numerator * 100" will have data overflow. */
477 numerator /= 1000;
478 denominator /= 1000;
479
480 return DIV_ROUND_UP(numerator * 100, denominator);
481 }
482
svs_readl_relaxed(struct svs_platform * svsp,enum svs_reg_index rg_i)483 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i)
484 {
485 return readl_relaxed(svsp->base + svsp->regs[rg_i]);
486 }
487
svs_writel_relaxed(struct svs_platform * svsp,u32 val,enum svs_reg_index rg_i)488 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,
489 enum svs_reg_index rg_i)
490 {
491 writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
492 }
493
svs_switch_bank(struct svs_platform * svsp)494 static void svs_switch_bank(struct svs_platform *svsp)
495 {
496 struct svs_bank *svsb = svsp->pbank;
497
498 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
499 }
500
svs_bank_volt_to_opp_volt(u32 svsb_volt,u32 svsb_volt_step,u32 svsb_volt_base)501 static u32 svs_bank_volt_to_opp_volt(u32 svsb_volt, u32 svsb_volt_step,
502 u32 svsb_volt_base)
503 {
504 return (svsb_volt * svsb_volt_step) + svsb_volt_base;
505 }
506
svs_opp_volt_to_bank_volt(u32 opp_u_volt,u32 svsb_volt_step,u32 svsb_volt_base)507 static u32 svs_opp_volt_to_bank_volt(u32 opp_u_volt, u32 svsb_volt_step,
508 u32 svsb_volt_base)
509 {
510 return (opp_u_volt - svsb_volt_base) / svsb_volt_step;
511 }
512
svs_sync_bank_volts_from_opp(struct svs_bank * svsb)513 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb)
514 {
515 struct dev_pm_opp *opp;
516 u32 i, opp_u_volt;
517
518 for (i = 0; i < svsb->opp_count; i++) {
519 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
520 svsb->opp_dfreq[i],
521 true);
522 if (IS_ERR(opp)) {
523 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
524 svsb->opp_dfreq[i], PTR_ERR(opp));
525 return PTR_ERR(opp);
526 }
527
528 opp_u_volt = dev_pm_opp_get_voltage(opp);
529 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
530 svsb->volt_step,
531 svsb->volt_base);
532 dev_pm_opp_put(opp);
533 }
534
535 return 0;
536 }
537
svs_adjust_pm_opp_volts(struct svs_bank * svsb)538 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
539 {
540 int ret = -EPERM, tzone_temp = 0;
541 u32 i, svsb_volt, opp_volt, temp_voffset = 0, opp_start, opp_stop;
542
543 mutex_lock(&svsb->lock);
544
545 /*
546 * 2-line bank updates its corresponding opp volts.
547 * 1-line bank updates all opp volts.
548 */
549 if (svsb->type == SVSB_HIGH) {
550 opp_start = 0;
551 opp_stop = svsb->turn_pt;
552 } else if (svsb->type == SVSB_LOW) {
553 opp_start = svsb->turn_pt;
554 opp_stop = svsb->opp_count;
555 } else {
556 opp_start = 0;
557 opp_stop = svsb->opp_count;
558 }
559
560 /* Get thermal effect */
561 if (svsb->phase == SVSB_PHASE_MON) {
562 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
563 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
564 svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
565 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
566 svsb->tzone_name, ret, svsb->temp);
567 svsb->phase = SVSB_PHASE_ERROR;
568 }
569
570 if (tzone_temp >= svsb->tzone_htemp)
571 temp_voffset += svsb->tzone_htemp_voffset;
572 else if (tzone_temp <= svsb->tzone_ltemp)
573 temp_voffset += svsb->tzone_ltemp_voffset;
574
575 /* 2-line bank update all opp volts when running mon mode */
576 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) {
577 opp_start = 0;
578 opp_stop = svsb->opp_count;
579 }
580 }
581
582 /* vmin <= svsb_volt (opp_volt) <= default opp voltage */
583 for (i = opp_start; i < opp_stop; i++) {
584 switch (svsb->phase) {
585 case SVSB_PHASE_ERROR:
586 opp_volt = svsb->opp_dvolt[i];
587 break;
588 case SVSB_PHASE_INIT01:
589 /* do nothing */
590 goto unlock_mutex;
591 case SVSB_PHASE_INIT02:
592 svsb_volt = max(svsb->volt[i], svsb->vmin);
593 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt,
594 svsb->volt_step,
595 svsb->volt_base);
596 break;
597 case SVSB_PHASE_MON:
598 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
599 opp_volt = svs_bank_volt_to_opp_volt(svsb_volt,
600 svsb->volt_step,
601 svsb->volt_base);
602 break;
603 default:
604 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
605 ret = -EINVAL;
606 goto unlock_mutex;
607 }
608
609 opp_volt = min(opp_volt, svsb->opp_dvolt[i]);
610 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
611 svsb->opp_dfreq[i],
612 opp_volt, opp_volt,
613 svsb->opp_dvolt[i]);
614 if (ret) {
615 dev_err(svsb->dev, "set %uuV fail: %d\n",
616 opp_volt, ret);
617 goto unlock_mutex;
618 }
619 }
620
621 unlock_mutex:
622 mutex_unlock(&svsb->lock);
623
624 return ret;
625 }
626
627 #ifdef CONFIG_DEBUG_FS
svs_dump_debug_show(struct seq_file * m,void * p)628 static int svs_dump_debug_show(struct seq_file *m, void *p)
629 {
630 struct svs_platform *svsp = (struct svs_platform *)m->private;
631 struct svs_bank *svsb;
632 unsigned long svs_reg_addr;
633 u32 idx, i, j, bank_id;
634
635 for (i = 0; i < svsp->efuse_max; i++)
636 if (svsp->efuse && svsp->efuse[i])
637 seq_printf(m, "M_HW_RES%d = 0x%08x\n",
638 i, svsp->efuse[i]);
639
640 for (i = 0; i < svsp->tefuse_max; i++)
641 if (svsp->tefuse)
642 seq_printf(m, "THERMAL_EFUSE%d = 0x%08x\n",
643 i, svsp->tefuse[i]);
644
645 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
646 svsb = &svsp->banks[idx];
647
648 for (i = SVSB_PHASE_INIT01; i <= SVSB_PHASE_MON; i++) {
649 seq_printf(m, "Bank_number = %u\n", bank_id);
650
651 if (i == SVSB_PHASE_INIT01 || i == SVSB_PHASE_INIT02)
652 seq_printf(m, "mode = init%d\n", i);
653 else if (i == SVSB_PHASE_MON)
654 seq_puts(m, "mode = mon\n");
655 else
656 seq_puts(m, "mode = error\n");
657
658 for (j = DESCHAR; j < SVS_REG_MAX; j++) {
659 svs_reg_addr = (unsigned long)(svsp->base +
660 svsp->regs[j]);
661 seq_printf(m, "0x%08lx = 0x%08x\n",
662 svs_reg_addr, svsb->reg_data[i][j]);
663 }
664 }
665 }
666
667 return 0;
668 }
669
670 debug_fops_ro(dump);
671
svs_enable_debug_show(struct seq_file * m,void * v)672 static int svs_enable_debug_show(struct seq_file *m, void *v)
673 {
674 struct svs_bank *svsb = (struct svs_bank *)m->private;
675
676 switch (svsb->phase) {
677 case SVSB_PHASE_ERROR:
678 seq_puts(m, "disabled\n");
679 break;
680 case SVSB_PHASE_INIT01:
681 seq_puts(m, "init1\n");
682 break;
683 case SVSB_PHASE_INIT02:
684 seq_puts(m, "init2\n");
685 break;
686 case SVSB_PHASE_MON:
687 seq_puts(m, "mon mode\n");
688 break;
689 default:
690 seq_puts(m, "unknown\n");
691 break;
692 }
693
694 return 0;
695 }
696
svs_enable_debug_write(struct file * filp,const char __user * buffer,size_t count,loff_t * pos)697 static ssize_t svs_enable_debug_write(struct file *filp,
698 const char __user *buffer,
699 size_t count, loff_t *pos)
700 {
701 struct svs_bank *svsb = file_inode(filp)->i_private;
702 struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
703 unsigned long flags;
704 int enabled, ret;
705 char *buf = NULL;
706
707 if (count >= PAGE_SIZE)
708 return -EINVAL;
709
710 buf = (char *)memdup_user_nul(buffer, count);
711 if (IS_ERR(buf))
712 return PTR_ERR(buf);
713
714 ret = kstrtoint(buf, 10, &enabled);
715 if (ret)
716 return ret;
717
718 if (!enabled) {
719 spin_lock_irqsave(&svs_lock, flags);
720 svsp->pbank = svsb;
721 svsb->mode_support = SVSB_MODE_ALL_DISABLE;
722 svs_switch_bank(svsp);
723 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
724 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
725 spin_unlock_irqrestore(&svs_lock, flags);
726
727 svsb->phase = SVSB_PHASE_ERROR;
728 svs_adjust_pm_opp_volts(svsb);
729 }
730
731 kfree(buf);
732
733 return count;
734 }
735
736 debug_fops_rw(enable);
737
svs_status_debug_show(struct seq_file * m,void * v)738 static int svs_status_debug_show(struct seq_file *m, void *v)
739 {
740 struct svs_bank *svsb = (struct svs_bank *)m->private;
741 struct dev_pm_opp *opp;
742 int tzone_temp = 0, ret;
743 u32 i;
744
745 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
746 if (ret)
747 seq_printf(m, "%s: temperature ignore, turn_pt = %u\n",
748 svsb->name, svsb->turn_pt);
749 else
750 seq_printf(m, "%s: temperature = %d, turn_pt = %u\n",
751 svsb->name, tzone_temp, svsb->turn_pt);
752
753 for (i = 0; i < svsb->opp_count; i++) {
754 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
755 svsb->opp_dfreq[i], true);
756 if (IS_ERR(opp)) {
757 seq_printf(m, "%s: cannot find freq = %u (%ld)\n",
758 svsb->name, svsb->opp_dfreq[i],
759 PTR_ERR(opp));
760 return PTR_ERR(opp);
761 }
762
763 seq_printf(m, "opp_freq[%02u]: %u, opp_volt[%02u]: %lu, ",
764 i, svsb->opp_dfreq[i], i,
765 dev_pm_opp_get_voltage(opp));
766 seq_printf(m, "svsb_volt[%02u]: 0x%x, freq_pct[%02u]: %u\n",
767 i, svsb->volt[i], i, svsb->freq_pct[i]);
768 dev_pm_opp_put(opp);
769 }
770
771 return 0;
772 }
773
774 debug_fops_ro(status);
775
svs_create_debug_cmds(struct svs_platform * svsp)776 static int svs_create_debug_cmds(struct svs_platform *svsp)
777 {
778 struct svs_bank *svsb;
779 struct dentry *svs_dir, *svsb_dir, *file_entry;
780 const char *d = "/sys/kernel/debug/svs";
781 u32 i, idx;
782
783 struct svs_dentry {
784 const char *name;
785 const struct file_operations *fops;
786 };
787
788 struct svs_dentry svs_entries[] = {
789 svs_dentry_data(dump),
790 };
791
792 struct svs_dentry svsb_entries[] = {
793 svs_dentry_data(enable),
794 svs_dentry_data(status),
795 };
796
797 svs_dir = debugfs_create_dir("svs", NULL);
798 if (IS_ERR(svs_dir)) {
799 dev_err(svsp->dev, "cannot create %s: %ld\n",
800 d, PTR_ERR(svs_dir));
801 return PTR_ERR(svs_dir);
802 }
803
804 for (i = 0; i < ARRAY_SIZE(svs_entries); i++) {
805 file_entry = debugfs_create_file(svs_entries[i].name, 0664,
806 svs_dir, svsp,
807 svs_entries[i].fops);
808 if (IS_ERR(file_entry)) {
809 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
810 d, svs_entries[i].name, PTR_ERR(file_entry));
811 return PTR_ERR(file_entry);
812 }
813 }
814
815 for (idx = 0; idx < svsp->bank_max; idx++) {
816 svsb = &svsp->banks[idx];
817
818 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
819 continue;
820
821 svsb_dir = debugfs_create_dir(svsb->name, svs_dir);
822 if (IS_ERR(svsb_dir)) {
823 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
824 d, svsb->name, PTR_ERR(svsb_dir));
825 return PTR_ERR(svsb_dir);
826 }
827
828 for (i = 0; i < ARRAY_SIZE(svsb_entries); i++) {
829 file_entry = debugfs_create_file(svsb_entries[i].name,
830 0664, svsb_dir, svsb,
831 svsb_entries[i].fops);
832 if (IS_ERR(file_entry)) {
833 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
834 d, svsb->name, svsb_entries[i].name,
835 PTR_ERR(file_entry));
836 return PTR_ERR(file_entry);
837 }
838 }
839 }
840
841 return 0;
842 }
843 #endif /* CONFIG_DEBUG_FS */
844
interpolate(u32 f0,u32 f1,u32 v0,u32 v1,u32 fx)845 static u32 interpolate(u32 f0, u32 f1, u32 v0, u32 v1, u32 fx)
846 {
847 u32 vx;
848
849 if (v0 == v1 || f0 == f1)
850 return v0;
851
852 /* *100 to have decimal fraction factor */
853 vx = (v0 * 100) - ((((v0 - v1) * 100) / (f0 - f1)) * (f0 - fx));
854
855 return DIV_ROUND_UP(vx, 100);
856 }
857
svs_get_bank_volts_v3(struct svs_platform * svsp)858 static void svs_get_bank_volts_v3(struct svs_platform *svsp)
859 {
860 struct svs_bank *svsb = svsp->pbank;
861 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
862 u32 b_sft, shift_byte = 0, opp_start = 0, opp_stop = 0;
863 u32 middle_index = (svsb->opp_count / 2);
864
865 if (svsb->phase == SVSB_PHASE_MON &&
866 svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
867 return;
868
869 vop74 = svs_readl_relaxed(svsp, VOP74);
870 vop30 = svs_readl_relaxed(svsp, VOP30);
871
872 /* Target is to set svsb->volt[] by algorithm */
873 if (turn_pt < middle_index) {
874 if (svsb->type == SVSB_HIGH) {
875 /* volt[0] ~ volt[turn_pt - 1] */
876 for (i = 0; i < turn_pt; i++) {
877 b_sft = BITS8 * (shift_byte % REG_BYTES);
878 vop = (shift_byte < REG_BYTES) ? &vop30 :
879 &vop74;
880 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
881 shift_byte++;
882 }
883 } else if (svsb->type == SVSB_LOW) {
884 /* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
885 j = svsb->opp_count - 7;
886 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
887 shift_byte++;
888 for (i = j; i < svsb->opp_count; i++) {
889 b_sft = BITS8 * (shift_byte % REG_BYTES);
890 vop = (shift_byte < REG_BYTES) ? &vop30 :
891 &vop74;
892 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
893 shift_byte++;
894 }
895
896 /* volt[turn_pt + 1] ~ volt[j - 1] by interpolate */
897 for (i = turn_pt + 1; i < j; i++)
898 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt],
899 svsb->freq_pct[j],
900 svsb->volt[turn_pt],
901 svsb->volt[j],
902 svsb->freq_pct[i]);
903 }
904 } else {
905 if (svsb->type == SVSB_HIGH) {
906 /* volt[0] + volt[j] ~ volt[turn_pt - 1] */
907 j = turn_pt - 7;
908 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
909 shift_byte++;
910 for (i = j; i < turn_pt; i++) {
911 b_sft = BITS8 * (shift_byte % REG_BYTES);
912 vop = (shift_byte < REG_BYTES) ? &vop30 :
913 &vop74;
914 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
915 shift_byte++;
916 }
917
918 /* volt[1] ~ volt[j - 1] by interpolate */
919 for (i = 1; i < j; i++)
920 svsb->volt[i] = interpolate(svsb->freq_pct[0],
921 svsb->freq_pct[j],
922 svsb->volt[0],
923 svsb->volt[j],
924 svsb->freq_pct[i]);
925 } else if (svsb->type == SVSB_LOW) {
926 /* volt[turn_pt] ~ volt[opp_count - 1] */
927 for (i = turn_pt; i < svsb->opp_count; i++) {
928 b_sft = BITS8 * (shift_byte % REG_BYTES);
929 vop = (shift_byte < REG_BYTES) ? &vop30 :
930 &vop74;
931 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
932 shift_byte++;
933 }
934 }
935 }
936
937 if (svsb->type == SVSB_HIGH) {
938 opp_start = 0;
939 opp_stop = svsb->turn_pt;
940 } else if (svsb->type == SVSB_LOW) {
941 opp_start = svsb->turn_pt;
942 opp_stop = svsb->opp_count;
943 }
944
945 for (i = opp_start; i < opp_stop; i++)
946 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
947 svsb->volt[i] -= svsb->dvt_fixed;
948 }
949
svs_set_bank_freq_pct_v3(struct svs_platform * svsp)950 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp)
951 {
952 struct svs_bank *svsb = svsp->pbank;
953 u32 i, j, *freq_pct, freq_pct74 = 0, freq_pct30 = 0;
954 u32 b_sft, shift_byte = 0, turn_pt;
955 u32 middle_index = (svsb->opp_count / 2);
956
957 for (i = 0; i < svsb->opp_count; i++) {
958 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) {
959 svsb->turn_pt = i;
960 break;
961 }
962 }
963
964 turn_pt = svsb->turn_pt;
965
966 /* Target is to fill out freq_pct74 / freq_pct30 by algorithm */
967 if (turn_pt < middle_index) {
968 if (svsb->type == SVSB_HIGH) {
969 /*
970 * If we don't handle this situation,
971 * SVSB_HIGH's FREQPCT74 / FREQPCT30 would keep "0"
972 * and this leads SVSB_LOW to work abnormally.
973 */
974 if (turn_pt == 0)
975 freq_pct30 = svsb->freq_pct[0];
976
977 /* freq_pct[0] ~ freq_pct[turn_pt - 1] */
978 for (i = 0; i < turn_pt; i++) {
979 b_sft = BITS8 * (shift_byte % REG_BYTES);
980 freq_pct = (shift_byte < REG_BYTES) ?
981 &freq_pct30 : &freq_pct74;
982 *freq_pct |= (svsb->freq_pct[i] << b_sft);
983 shift_byte++;
984 }
985 } else if (svsb->type == SVSB_LOW) {
986 /*
987 * freq_pct[turn_pt] +
988 * freq_pct[opp_count - 7] ~ freq_pct[opp_count -1]
989 */
990 freq_pct30 = svsb->freq_pct[turn_pt];
991 shift_byte++;
992 j = svsb->opp_count - 7;
993 for (i = j; i < svsb->opp_count; i++) {
994 b_sft = BITS8 * (shift_byte % REG_BYTES);
995 freq_pct = (shift_byte < REG_BYTES) ?
996 &freq_pct30 : &freq_pct74;
997 *freq_pct |= (svsb->freq_pct[i] << b_sft);
998 shift_byte++;
999 }
1000 }
1001 } else {
1002 if (svsb->type == SVSB_HIGH) {
1003 /*
1004 * freq_pct[0] +
1005 * freq_pct[turn_pt - 7] ~ freq_pct[turn_pt - 1]
1006 */
1007 freq_pct30 = svsb->freq_pct[0];
1008 shift_byte++;
1009 j = turn_pt - 7;
1010 for (i = j; i < turn_pt; i++) {
1011 b_sft = BITS8 * (shift_byte % REG_BYTES);
1012 freq_pct = (shift_byte < REG_BYTES) ?
1013 &freq_pct30 : &freq_pct74;
1014 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1015 shift_byte++;
1016 }
1017 } else if (svsb->type == SVSB_LOW) {
1018 /* freq_pct[turn_pt] ~ freq_pct[opp_count - 1] */
1019 for (i = turn_pt; i < svsb->opp_count; i++) {
1020 b_sft = BITS8 * (shift_byte % REG_BYTES);
1021 freq_pct = (shift_byte < REG_BYTES) ?
1022 &freq_pct30 : &freq_pct74;
1023 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1024 shift_byte++;
1025 }
1026 }
1027 }
1028
1029 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);
1030 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);
1031 }
1032
svs_get_bank_volts_v2(struct svs_platform * svsp)1033 static void svs_get_bank_volts_v2(struct svs_platform *svsp)
1034 {
1035 struct svs_bank *svsb = svsp->pbank;
1036 u32 temp, i;
1037
1038 temp = svs_readl_relaxed(svsp, VOP74);
1039 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1040 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1041 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1042 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1043
1044 temp = svs_readl_relaxed(svsp, VOP30);
1045 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1046 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1047 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1048 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1049
1050 for (i = 0; i <= 12; i += 2)
1051 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i],
1052 svsb->freq_pct[i + 2],
1053 svsb->volt[i],
1054 svsb->volt[i + 2],
1055 svsb->freq_pct[i + 1]);
1056
1057 svsb->volt[15] = interpolate(svsb->freq_pct[12],
1058 svsb->freq_pct[14],
1059 svsb->volt[12],
1060 svsb->volt[14],
1061 svsb->freq_pct[15]);
1062
1063 for (i = 0; i < svsb->opp_count; i++)
1064 svsb->volt[i] += svsb->volt_od;
1065 }
1066
svs_set_bank_freq_pct_v2(struct svs_platform * svsp)1067 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp)
1068 {
1069 struct svs_bank *svsb = svsp->pbank;
1070 u32 freqpct74_val, freqpct30_val;
1071
1072 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
1073 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
1074 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
1075 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
1076
1077 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
1078 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
1079 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
1080 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
1081
1082 svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);
1083 svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);
1084 }
1085
svs_set_bank_phase(struct svs_platform * svsp,enum svsb_phase target_phase)1086 static void svs_set_bank_phase(struct svs_platform *svsp,
1087 enum svsb_phase target_phase)
1088 {
1089 struct svs_bank *svsb = svsp->pbank;
1090 u32 des_char, temp_char, det_char, limit_vals, init2vals, ts_calcs;
1091
1092 svs_switch_bank(svsp);
1093
1094 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
1095 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
1096 svs_writel_relaxed(svsp, des_char, DESCHAR);
1097
1098 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) |
1099 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
1100 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
1101 svs_writel_relaxed(svsp, temp_char, TEMPCHAR);
1102
1103 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
1104 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
1105 svs_writel_relaxed(svsp, det_char, DETCHAR);
1106
1107 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG);
1108 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG);
1109 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG);
1110
1111 svsb->set_freq_pct(svsp);
1112
1113 limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) |
1114 FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) |
1115 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
1116 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
1117 svs_writel_relaxed(svsp, limit_vals, LIMITVALS);
1118
1119 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);
1120 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
1121 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT);
1122 svs_writel_relaxed(svsp, svsb->ctl0, CTL0);
1123 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1124
1125 switch (target_phase) {
1126 case SVSB_PHASE_INIT01:
1127 svs_writel_relaxed(svsp, svsb->vboot, VBOOT);
1128 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1129 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);
1130 break;
1131 case SVSB_PHASE_INIT02:
1132 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
1133 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
1134 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1135 svs_writel_relaxed(svsp, init2vals, INIT2VALS);
1136 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);
1137 break;
1138 case SVSB_PHASE_MON:
1139 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
1140 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
1141 svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
1142 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
1143 svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);
1144 break;
1145 default:
1146 dev_err(svsb->dev, "requested unknown target phase: %u\n",
1147 target_phase);
1148 break;
1149 }
1150 }
1151
svs_save_bank_register_data(struct svs_platform * svsp,enum svsb_phase phase)1152 static inline void svs_save_bank_register_data(struct svs_platform *svsp,
1153 enum svsb_phase phase)
1154 {
1155 struct svs_bank *svsb = svsp->pbank;
1156 enum svs_reg_index rg_i;
1157
1158 for (rg_i = DESCHAR; rg_i < SVS_REG_MAX; rg_i++)
1159 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1160 }
1161
svs_error_isr_handler(struct svs_platform * svsp)1162 static inline void svs_error_isr_handler(struct svs_platform *svsp)
1163 {
1164 struct svs_bank *svsb = svsp->pbank;
1165
1166 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n",
1167 __func__, svs_readl_relaxed(svsp, CORESEL));
1168 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n",
1169 svs_readl_relaxed(svsp, SVSEN),
1170 svs_readl_relaxed(svsp, INTSTS));
1171 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
1172 svs_readl_relaxed(svsp, SMSTATE0),
1173 svs_readl_relaxed(svsp, SMSTATE1));
1174 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1175
1176 svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR);
1177
1178 svsb->phase = SVSB_PHASE_ERROR;
1179 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1180 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1181 }
1182
svs_init01_isr_handler(struct svs_platform * svsp)1183 static inline void svs_init01_isr_handler(struct svs_platform *svsp)
1184 {
1185 struct svs_bank *svsb = svsp->pbank;
1186
1187 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n",
1188 __func__, svs_readl_relaxed(svsp, VDESIGN74),
1189 svs_readl_relaxed(svsp, VDESIGN30),
1190 svs_readl_relaxed(svsp, DCVALUES));
1191
1192 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01);
1193
1194 svsb->phase = SVSB_PHASE_INIT01;
1195 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) &
1196 GENMASK(15, 0)) + 1;
1197 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE ||
1198 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT &&
1199 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY))
1200 svsb->dc_voffset_in = 0;
1201
1202 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1203 GENMASK(15, 0);
1204
1205 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1206 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1207 svsb->core_sel &= ~SVSB_DET_CLK_EN;
1208 }
1209
svs_init02_isr_handler(struct svs_platform * svsp)1210 static inline void svs_init02_isr_handler(struct svs_platform *svsp)
1211 {
1212 struct svs_bank *svsb = svsp->pbank;
1213
1214 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n",
1215 __func__, svs_readl_relaxed(svsp, VOP74),
1216 svs_readl_relaxed(svsp, VOP30),
1217 svs_readl_relaxed(svsp, DCVALUES));
1218
1219 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02);
1220
1221 svsb->phase = SVSB_PHASE_INIT02;
1222 svsb->get_volts(svsp);
1223
1224 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1225 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1226 }
1227
svs_mon_mode_isr_handler(struct svs_platform * svsp)1228 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp)
1229 {
1230 struct svs_bank *svsb = svsp->pbank;
1231
1232 svs_save_bank_register_data(svsp, SVSB_PHASE_MON);
1233
1234 svsb->phase = SVSB_PHASE_MON;
1235 svsb->get_volts(svsp);
1236
1237 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1238 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);
1239 }
1240
svs_isr(int irq,void * data)1241 static irqreturn_t svs_isr(int irq, void *data)
1242 {
1243 struct svs_platform *svsp = data;
1244 struct svs_bank *svsb = NULL;
1245 unsigned long flags;
1246 u32 idx, int_sts, svs_en;
1247
1248 for (idx = 0; idx < svsp->bank_max; idx++) {
1249 svsb = &svsp->banks[idx];
1250 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name);
1251
1252 spin_lock_irqsave(&svs_lock, flags);
1253 svsp->pbank = svsb;
1254
1255 /* Find out which svs bank fires interrupt */
1256 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) {
1257 spin_unlock_irqrestore(&svs_lock, flags);
1258 continue;
1259 }
1260
1261 svs_switch_bank(svsp);
1262 int_sts = svs_readl_relaxed(svsp, INTSTS);
1263 svs_en = svs_readl_relaxed(svsp, SVSEN);
1264
1265 if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1266 svs_en == SVSB_PTPEN_INIT01)
1267 svs_init01_isr_handler(svsp);
1268 else if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
1269 svs_en == SVSB_PTPEN_INIT02)
1270 svs_init02_isr_handler(svsp);
1271 else if (int_sts & SVSB_INTSTS_FLD_MONVOP)
1272 svs_mon_mode_isr_handler(svsp);
1273 else
1274 svs_error_isr_handler(svsp);
1275
1276 spin_unlock_irqrestore(&svs_lock, flags);
1277 break;
1278 }
1279
1280 svs_adjust_pm_opp_volts(svsb);
1281
1282 if (svsb->phase == SVSB_PHASE_INIT01 ||
1283 svsb->phase == SVSB_PHASE_INIT02)
1284 complete(&svsb->init_completion);
1285
1286 return IRQ_HANDLED;
1287 }
1288
svs_init01(struct svs_platform * svsp)1289 static int svs_init01(struct svs_platform *svsp)
1290 {
1291 struct svs_bank *svsb;
1292 unsigned long flags, time_left;
1293 bool search_done;
1294 int ret = 0, r;
1295 u32 opp_freq, opp_vboot, buck_volt, idx, i;
1296
1297 /* Keep CPUs' core power on for svs_init01 initialization */
1298 cpuidle_pause_and_lock();
1299
1300 /* Svs bank init01 preparation - power enable */
1301 for (idx = 0; idx < svsp->bank_max; idx++) {
1302 svsb = &svsp->banks[idx];
1303
1304 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1305 continue;
1306
1307 ret = regulator_enable(svsb->buck);
1308 if (ret) {
1309 dev_err(svsb->dev, "%s enable fail: %d\n",
1310 svsb->buck_name, ret);
1311 goto svs_init01_resume_cpuidle;
1312 }
1313
1314 /* Some buck doesn't support mode change. Show fail msg only */
1315 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST);
1316 if (ret)
1317 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret);
1318
1319 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1320 if (!pm_runtime_enabled(svsb->opp_dev)) {
1321 pm_runtime_enable(svsb->opp_dev);
1322 svsb->pm_runtime_enabled_count++;
1323 }
1324
1325 ret = pm_runtime_resume_and_get(svsb->opp_dev);
1326 if (ret < 0) {
1327 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
1328 goto svs_init01_resume_cpuidle;
1329 }
1330 }
1331 }
1332
1333 /*
1334 * Svs bank init01 preparation - vboot voltage adjustment
1335 * Sometimes two svs banks use the same buck. Therefore,
1336 * we have to set each svs bank to target voltage(vboot) first.
1337 */
1338 for (idx = 0; idx < svsp->bank_max; idx++) {
1339 svsb = &svsp->banks[idx];
1340
1341 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1342 continue;
1343
1344 /*
1345 * Find the fastest freq that can be run at vboot and
1346 * fix to that freq until svs_init01 is done.
1347 */
1348 search_done = false;
1349 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot,
1350 svsb->volt_step,
1351 svsb->volt_base);
1352
1353 for (i = 0; i < svsb->opp_count; i++) {
1354 opp_freq = svsb->opp_dfreq[i];
1355 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) {
1356 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
1357 opp_freq,
1358 opp_vboot,
1359 opp_vboot,
1360 opp_vboot);
1361 if (ret) {
1362 dev_err(svsb->dev,
1363 "set opp %uuV vboot fail: %d\n",
1364 opp_vboot, ret);
1365 goto svs_init01_finish;
1366 }
1367
1368 search_done = true;
1369 } else {
1370 ret = dev_pm_opp_disable(svsb->opp_dev,
1371 svsb->opp_dfreq[i]);
1372 if (ret) {
1373 dev_err(svsb->dev,
1374 "opp %uHz disable fail: %d\n",
1375 svsb->opp_dfreq[i], ret);
1376 goto svs_init01_finish;
1377 }
1378 }
1379 }
1380 }
1381
1382 /* Svs bank init01 begins */
1383 for (idx = 0; idx < svsp->bank_max; idx++) {
1384 svsb = &svsp->banks[idx];
1385
1386 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1387 continue;
1388
1389 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot,
1390 svsb->volt_step,
1391 svsb->volt_base);
1392
1393 buck_volt = regulator_get_voltage(svsb->buck);
1394 if (buck_volt != opp_vboot) {
1395 dev_err(svsb->dev,
1396 "buck voltage: %uuV, expected vboot: %uuV\n",
1397 buck_volt, opp_vboot);
1398 ret = -EPERM;
1399 goto svs_init01_finish;
1400 }
1401
1402 spin_lock_irqsave(&svs_lock, flags);
1403 svsp->pbank = svsb;
1404 svs_set_bank_phase(svsp, SVSB_PHASE_INIT01);
1405 spin_unlock_irqrestore(&svs_lock, flags);
1406
1407 time_left = wait_for_completion_timeout(&svsb->init_completion,
1408 msecs_to_jiffies(5000));
1409 if (!time_left) {
1410 dev_err(svsb->dev, "init01 completion timeout\n");
1411 ret = -EBUSY;
1412 goto svs_init01_finish;
1413 }
1414 }
1415
1416 svs_init01_finish:
1417 for (idx = 0; idx < svsp->bank_max; idx++) {
1418 svsb = &svsp->banks[idx];
1419
1420 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1421 continue;
1422
1423 for (i = 0; i < svsb->opp_count; i++) {
1424 r = dev_pm_opp_enable(svsb->opp_dev,
1425 svsb->opp_dfreq[i]);
1426 if (r)
1427 dev_err(svsb->dev, "opp %uHz enable fail: %d\n",
1428 svsb->opp_dfreq[i], r);
1429 }
1430
1431 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1432 r = pm_runtime_put_sync(svsb->opp_dev);
1433 if (r)
1434 dev_err(svsb->dev, "mtcmos off fail: %d\n", r);
1435
1436 if (svsb->pm_runtime_enabled_count > 0) {
1437 pm_runtime_disable(svsb->opp_dev);
1438 svsb->pm_runtime_enabled_count--;
1439 }
1440 }
1441
1442 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL);
1443 if (r)
1444 dev_notice(svsb->dev, "set normal mode fail: %d\n", r);
1445
1446 r = regulator_disable(svsb->buck);
1447 if (r)
1448 dev_err(svsb->dev, "%s disable fail: %d\n",
1449 svsb->buck_name, r);
1450 }
1451
1452 svs_init01_resume_cpuidle:
1453 cpuidle_resume_and_unlock();
1454
1455 return ret;
1456 }
1457
svs_init02(struct svs_platform * svsp)1458 static int svs_init02(struct svs_platform *svsp)
1459 {
1460 struct svs_bank *svsb;
1461 unsigned long flags, time_left;
1462 int ret;
1463 u32 idx;
1464
1465 for (idx = 0; idx < svsp->bank_max; idx++) {
1466 svsb = &svsp->banks[idx];
1467
1468 if (!(svsb->mode_support & SVSB_MODE_INIT02))
1469 continue;
1470
1471 reinit_completion(&svsb->init_completion);
1472 spin_lock_irqsave(&svs_lock, flags);
1473 svsp->pbank = svsb;
1474 svs_set_bank_phase(svsp, SVSB_PHASE_INIT02);
1475 spin_unlock_irqrestore(&svs_lock, flags);
1476
1477 time_left = wait_for_completion_timeout(&svsb->init_completion,
1478 msecs_to_jiffies(5000));
1479 if (!time_left) {
1480 dev_err(svsb->dev, "init02 completion timeout\n");
1481 ret = -EBUSY;
1482 goto out_of_init02;
1483 }
1484 }
1485
1486 /*
1487 * 2-line high/low bank update its corresponding opp voltages only.
1488 * Therefore, we sync voltages from opp for high/low bank voltages
1489 * consistency.
1490 */
1491 for (idx = 0; idx < svsp->bank_max; idx++) {
1492 svsb = &svsp->banks[idx];
1493
1494 if (!(svsb->mode_support & SVSB_MODE_INIT02))
1495 continue;
1496
1497 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) {
1498 if (svs_sync_bank_volts_from_opp(svsb)) {
1499 dev_err(svsb->dev, "sync volt fail\n");
1500 ret = -EPERM;
1501 goto out_of_init02;
1502 }
1503 }
1504 }
1505
1506 return 0;
1507
1508 out_of_init02:
1509 for (idx = 0; idx < svsp->bank_max; idx++) {
1510 svsb = &svsp->banks[idx];
1511
1512 spin_lock_irqsave(&svs_lock, flags);
1513 svsp->pbank = svsb;
1514 svs_switch_bank(svsp);
1515 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1516 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1517 spin_unlock_irqrestore(&svs_lock, flags);
1518
1519 svsb->phase = SVSB_PHASE_ERROR;
1520 svs_adjust_pm_opp_volts(svsb);
1521 }
1522
1523 return ret;
1524 }
1525
svs_mon_mode(struct svs_platform * svsp)1526 static void svs_mon_mode(struct svs_platform *svsp)
1527 {
1528 struct svs_bank *svsb;
1529 unsigned long flags;
1530 u32 idx;
1531
1532 for (idx = 0; idx < svsp->bank_max; idx++) {
1533 svsb = &svsp->banks[idx];
1534
1535 if (!(svsb->mode_support & SVSB_MODE_MON))
1536 continue;
1537
1538 spin_lock_irqsave(&svs_lock, flags);
1539 svsp->pbank = svsb;
1540 svs_set_bank_phase(svsp, SVSB_PHASE_MON);
1541 spin_unlock_irqrestore(&svs_lock, flags);
1542 }
1543 }
1544
svs_start(struct svs_platform * svsp)1545 static int svs_start(struct svs_platform *svsp)
1546 {
1547 int ret;
1548
1549 ret = svs_init01(svsp);
1550 if (ret)
1551 return ret;
1552
1553 ret = svs_init02(svsp);
1554 if (ret)
1555 return ret;
1556
1557 svs_mon_mode(svsp);
1558
1559 return 0;
1560 }
1561
svs_suspend(struct device * dev)1562 static int svs_suspend(struct device *dev)
1563 {
1564 struct svs_platform *svsp = dev_get_drvdata(dev);
1565 struct svs_bank *svsb;
1566 unsigned long flags;
1567 int ret;
1568 u32 idx;
1569
1570 for (idx = 0; idx < svsp->bank_max; idx++) {
1571 svsb = &svsp->banks[idx];
1572
1573 /* This might wait for svs_isr() process */
1574 spin_lock_irqsave(&svs_lock, flags);
1575 svsp->pbank = svsb;
1576 svs_switch_bank(svsp);
1577 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1578 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1579 spin_unlock_irqrestore(&svs_lock, flags);
1580
1581 svsb->phase = SVSB_PHASE_ERROR;
1582 svs_adjust_pm_opp_volts(svsb);
1583 }
1584
1585 ret = reset_control_assert(svsp->rst);
1586 if (ret) {
1587 dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1588 return ret;
1589 }
1590
1591 clk_disable_unprepare(svsp->main_clk);
1592
1593 return 0;
1594 }
1595
svs_resume(struct device * dev)1596 static int svs_resume(struct device *dev)
1597 {
1598 struct svs_platform *svsp = dev_get_drvdata(dev);
1599 int ret;
1600
1601 ret = clk_prepare_enable(svsp->main_clk);
1602 if (ret) {
1603 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1604 return ret;
1605 }
1606
1607 ret = reset_control_deassert(svsp->rst);
1608 if (ret) {
1609 dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1610 goto out_of_resume;
1611 }
1612
1613 ret = svs_init02(svsp);
1614 if (ret)
1615 goto svs_resume_reset_assert;
1616
1617 svs_mon_mode(svsp);
1618
1619 return 0;
1620
1621 svs_resume_reset_assert:
1622 dev_err(svsp->dev, "assert reset: %d\n",
1623 reset_control_assert(svsp->rst));
1624
1625 out_of_resume:
1626 clk_disable_unprepare(svsp->main_clk);
1627 return ret;
1628 }
1629
svs_bank_resource_setup(struct svs_platform * svsp)1630 static int svs_bank_resource_setup(struct svs_platform *svsp)
1631 {
1632 struct svs_bank *svsb;
1633 struct dev_pm_opp *opp;
1634 unsigned long freq;
1635 int count, ret;
1636 u32 idx, i;
1637
1638 dev_set_drvdata(svsp->dev, svsp);
1639
1640 for (idx = 0; idx < svsp->bank_max; idx++) {
1641 svsb = &svsp->banks[idx];
1642
1643 switch (svsb->sw_id) {
1644 case SVSB_CPU_LITTLE:
1645 svsb->name = "SVSB_CPU_LITTLE";
1646 break;
1647 case SVSB_CPU_BIG:
1648 svsb->name = "SVSB_CPU_BIG";
1649 break;
1650 case SVSB_CCI:
1651 svsb->name = "SVSB_CCI";
1652 break;
1653 case SVSB_GPU:
1654 if (svsb->type == SVSB_HIGH)
1655 svsb->name = "SVSB_GPU_HIGH";
1656 else if (svsb->type == SVSB_LOW)
1657 svsb->name = "SVSB_GPU_LOW";
1658 else
1659 svsb->name = "SVSB_GPU";
1660 break;
1661 default:
1662 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
1663 return -EINVAL;
1664 }
1665
1666 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev),
1667 GFP_KERNEL);
1668 if (!svsb->dev)
1669 return -ENOMEM;
1670
1671 ret = dev_set_name(svsb->dev, "%s", svsb->name);
1672 if (ret)
1673 return ret;
1674
1675 dev_set_drvdata(svsb->dev, svsp);
1676
1677 ret = devm_pm_opp_of_add_table(svsb->opp_dev);
1678 if (ret) {
1679 dev_err(svsb->dev, "add opp table fail: %d\n", ret);
1680 return ret;
1681 }
1682
1683 mutex_init(&svsb->lock);
1684 init_completion(&svsb->init_completion);
1685
1686 if (svsb->mode_support & SVSB_MODE_INIT01) {
1687 svsb->buck = devm_regulator_get_optional(svsb->opp_dev,
1688 svsb->buck_name);
1689 if (IS_ERR(svsb->buck)) {
1690 dev_err(svsb->dev, "cannot get \"%s-supply\"\n",
1691 svsb->buck_name);
1692 return PTR_ERR(svsb->buck);
1693 }
1694 }
1695
1696 if (svsb->mode_support & SVSB_MODE_MON) {
1697 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name);
1698 if (IS_ERR(svsb->tzd)) {
1699 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1700 svsb->tzone_name);
1701 return PTR_ERR(svsb->tzd);
1702 }
1703 }
1704
1705 count = dev_pm_opp_get_opp_count(svsb->opp_dev);
1706 if (svsb->opp_count != count) {
1707 dev_err(svsb->dev,
1708 "opp_count not \"%u\" but get \"%d\"?\n",
1709 svsb->opp_count, count);
1710 return count;
1711 }
1712
1713 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) {
1714 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq);
1715 if (IS_ERR(opp)) {
1716 dev_err(svsb->dev, "cannot find freq = %ld\n",
1717 PTR_ERR(opp));
1718 return PTR_ERR(opp);
1719 }
1720
1721 svsb->opp_dfreq[i] = freq;
1722 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp);
1723 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i],
1724 svsb->freq_base);
1725 dev_pm_opp_put(opp);
1726 }
1727 }
1728
1729 return 0;
1730 }
1731
svs_thermal_efuse_get_data(struct svs_platform * svsp)1732 static int svs_thermal_efuse_get_data(struct svs_platform *svsp)
1733 {
1734 struct nvmem_cell *cell;
1735
1736 /* Thermal efuse parsing */
1737 cell = nvmem_cell_get(svsp->dev, "t-calibration-data");
1738 if (IS_ERR_OR_NULL(cell)) {
1739 dev_err(svsp->dev, "no \"t-calibration-data\"? %ld\n", PTR_ERR(cell));
1740 return PTR_ERR(cell);
1741 }
1742
1743 svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_max);
1744 if (IS_ERR(svsp->tefuse)) {
1745 dev_err(svsp->dev, "cannot read thermal efuse: %ld\n",
1746 PTR_ERR(svsp->tefuse));
1747 nvmem_cell_put(cell);
1748 return PTR_ERR(svsp->tefuse);
1749 }
1750
1751 svsp->tefuse_max /= sizeof(u32);
1752 nvmem_cell_put(cell);
1753
1754 return 0;
1755 }
1756
svs_mt8192_efuse_parsing(struct svs_platform * svsp)1757 static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp)
1758 {
1759 struct svs_bank *svsb;
1760 u32 idx, i, vmin, golden_temp;
1761 int ret;
1762
1763 for (i = 0; i < svsp->efuse_max; i++)
1764 if (svsp->efuse[i])
1765 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1766 i, svsp->efuse[i]);
1767
1768 if (!svsp->efuse[9]) {
1769 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n");
1770 return false;
1771 }
1772
1773 /* Svs efuse parsing */
1774 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0);
1775
1776 for (idx = 0; idx < svsp->bank_max; idx++) {
1777 svsb = &svsp->banks[idx];
1778
1779 if (vmin == 0x1)
1780 svsb->vmin = 0x1e;
1781
1782 if (svsb->type == SVSB_LOW) {
1783 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0);
1784 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0);
1785 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0);
1786 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0);
1787 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0);
1788 } else if (svsb->type == SVSB_HIGH) {
1789 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0);
1790 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0);
1791 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0);
1792 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
1793 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0);
1794 }
1795
1796 svsb->vmax += svsb->dvt_fixed;
1797 }
1798
1799 ret = svs_thermal_efuse_get_data(svsp);
1800 if (ret)
1801 return false;
1802
1803 for (i = 0; i < svsp->tefuse_max; i++)
1804 if (svsp->tefuse[i] != 0)
1805 break;
1806
1807 if (i == svsp->tefuse_max)
1808 golden_temp = 50; /* All thermal efuse data are 0 */
1809 else
1810 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0);
1811
1812 for (idx = 0; idx < svsp->bank_max; idx++) {
1813 svsb = &svsp->banks[idx];
1814 svsb->mts = 500;
1815 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4;
1816 }
1817
1818 return true;
1819 }
1820
svs_mt8183_efuse_parsing(struct svs_platform * svsp)1821 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
1822 {
1823 struct svs_bank *svsb;
1824 int format[6], x_roomt[6], o_vtsmcu[5], o_vtsabb, tb_roomt = 0;
1825 int adc_ge_t, adc_oe_t, ge, oe, gain, degc_cali, adc_cali_en_t;
1826 int o_slope, o_slope_sign, ts_id;
1827 u32 idx, i, ft_pgm, mts, temp0, temp1, temp2;
1828 int ret;
1829
1830 for (i = 0; i < svsp->efuse_max; i++)
1831 if (svsp->efuse[i])
1832 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1833 i, svsp->efuse[i]);
1834
1835 if (!svsp->efuse[2]) {
1836 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1837 return false;
1838 }
1839
1840 /* Svs efuse parsing */
1841 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0);
1842
1843 for (idx = 0; idx < svsp->bank_max; idx++) {
1844 svsb = &svsp->banks[idx];
1845
1846 if (ft_pgm <= 1)
1847 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1848
1849 switch (svsb->sw_id) {
1850 case SVSB_CPU_LITTLE:
1851 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0);
1852 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0);
1853 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0);
1854 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0);
1855 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
1856
1857 if (ft_pgm <= 3)
1858 svsb->volt_od += 10;
1859 else
1860 svsb->volt_od += 2;
1861 break;
1862 case SVSB_CPU_BIG:
1863 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0);
1864 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0);
1865 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0);
1866 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0);
1867 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0);
1868
1869 if (ft_pgm <= 3)
1870 svsb->volt_od += 15;
1871 else
1872 svsb->volt_od += 12;
1873 break;
1874 case SVSB_CCI:
1875 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0);
1876 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0);
1877 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0);
1878 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0);
1879 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0);
1880
1881 if (ft_pgm <= 3)
1882 svsb->volt_od += 10;
1883 else
1884 svsb->volt_od += 2;
1885 break;
1886 case SVSB_GPU:
1887 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0);
1888 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0);
1889 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0);
1890 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0);
1891 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0);
1892
1893 if (ft_pgm >= 2) {
1894 svsb->freq_base = 800000000; /* 800MHz */
1895 svsb->dvt_fixed = 2;
1896 }
1897 break;
1898 default:
1899 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
1900 return false;
1901 }
1902 }
1903
1904 ret = svs_thermal_efuse_get_data(svsp);
1905 if (ret)
1906 return false;
1907
1908 /* Thermal efuse parsing */
1909 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
1910 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
1911
1912 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
1913 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
1914 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
1915 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
1916 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
1917 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
1918
1919 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
1920 adc_cali_en_t = svsp->tefuse[0] & BIT(0);
1921 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
1922
1923 ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
1924 if (!ts_id) {
1925 o_slope = 1534;
1926 } else {
1927 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
1928 if (!o_slope_sign)
1929 o_slope = 1534 + o_slope * 10;
1930 else
1931 o_slope = 1534 - o_slope * 10;
1932 }
1933
1934 if (adc_cali_en_t == 0 ||
1935 adc_ge_t < 265 || adc_ge_t > 758 ||
1936 adc_oe_t < 265 || adc_oe_t > 758 ||
1937 o_vtsmcu[0] < -8 || o_vtsmcu[0] > 484 ||
1938 o_vtsmcu[1] < -8 || o_vtsmcu[1] > 484 ||
1939 o_vtsmcu[2] < -8 || o_vtsmcu[2] > 484 ||
1940 o_vtsmcu[3] < -8 || o_vtsmcu[3] > 484 ||
1941 o_vtsmcu[4] < -8 || o_vtsmcu[4] > 484 ||
1942 o_vtsabb < -8 || o_vtsabb > 484 ||
1943 degc_cali < 1 || degc_cali > 63) {
1944 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
1945 goto remove_mt8183_svsb_mon_mode;
1946 }
1947
1948 ge = ((adc_ge_t - 512) * 10000) / 4096;
1949 oe = (adc_oe_t - 512);
1950 gain = (10000 + ge);
1951
1952 format[0] = (o_vtsmcu[0] + 3350 - oe);
1953 format[1] = (o_vtsmcu[1] + 3350 - oe);
1954 format[2] = (o_vtsmcu[2] + 3350 - oe);
1955 format[3] = (o_vtsmcu[3] + 3350 - oe);
1956 format[4] = (o_vtsmcu[4] + 3350 - oe);
1957 format[5] = (o_vtsabb + 3350 - oe);
1958
1959 for (i = 0; i < 6; i++)
1960 x_roomt[i] = (((format[i] * 10000) / 4096) * 10000) / gain;
1961
1962 temp0 = (10000 * 100000 / gain) * 15 / 18;
1963 mts = (temp0 * 10) / o_slope;
1964
1965 for (idx = 0; idx < svsp->bank_max; idx++) {
1966 svsb = &svsp->banks[idx];
1967 svsb->mts = mts;
1968
1969 switch (svsb->sw_id) {
1970 case SVSB_CPU_LITTLE:
1971 tb_roomt = x_roomt[3];
1972 break;
1973 case SVSB_CPU_BIG:
1974 tb_roomt = x_roomt[4];
1975 break;
1976 case SVSB_CCI:
1977 tb_roomt = x_roomt[3];
1978 break;
1979 case SVSB_GPU:
1980 tb_roomt = x_roomt[1];
1981 break;
1982 default:
1983 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
1984 goto remove_mt8183_svsb_mon_mode;
1985 }
1986
1987 temp0 = (degc_cali * 10 / 2);
1988 temp1 = ((10000 * 100000 / 4096 / gain) *
1989 oe + tb_roomt * 10) * 15 / 18;
1990 temp2 = temp1 * 100 / o_slope;
1991
1992 svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
1993 }
1994
1995 return true;
1996
1997 remove_mt8183_svsb_mon_mode:
1998 for (idx = 0; idx < svsp->bank_max; idx++) {
1999 svsb = &svsp->banks[idx];
2000 svsb->mode_support &= ~SVSB_MODE_MON;
2001 }
2002
2003 return true;
2004 }
2005
svs_is_efuse_data_correct(struct svs_platform * svsp)2006 static bool svs_is_efuse_data_correct(struct svs_platform *svsp)
2007 {
2008 struct nvmem_cell *cell;
2009
2010 /* Get svs efuse by nvmem */
2011 cell = nvmem_cell_get(svsp->dev, "svs-calibration-data");
2012 if (IS_ERR(cell)) {
2013 dev_err(svsp->dev, "no \"svs-calibration-data\"? %ld\n",
2014 PTR_ERR(cell));
2015 return false;
2016 }
2017
2018 svsp->efuse = nvmem_cell_read(cell, &svsp->efuse_max);
2019 if (IS_ERR(svsp->efuse)) {
2020 dev_err(svsp->dev, "cannot read svs efuse: %ld\n",
2021 PTR_ERR(svsp->efuse));
2022 nvmem_cell_put(cell);
2023 return false;
2024 }
2025
2026 svsp->efuse_max /= sizeof(u32);
2027 nvmem_cell_put(cell);
2028
2029 return true;
2030 }
2031
svs_get_subsys_device(struct svs_platform * svsp,const char * node_name)2032 static struct device *svs_get_subsys_device(struct svs_platform *svsp,
2033 const char *node_name)
2034 {
2035 struct platform_device *pdev;
2036 struct device_node *np;
2037
2038 np = of_find_node_by_name(NULL, node_name);
2039 if (!np) {
2040 dev_err(svsp->dev, "cannot find %s node\n", node_name);
2041 return ERR_PTR(-ENODEV);
2042 }
2043
2044 pdev = of_find_device_by_node(np);
2045 if (!pdev) {
2046 of_node_put(np);
2047 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2048 return ERR_PTR(-ENXIO);
2049 }
2050
2051 of_node_put(np);
2052
2053 return &pdev->dev;
2054 }
2055
svs_add_device_link(struct svs_platform * svsp,const char * node_name)2056 static struct device *svs_add_device_link(struct svs_platform *svsp,
2057 const char *node_name)
2058 {
2059 struct device *dev;
2060 struct device_link *sup_link;
2061
2062 if (!node_name) {
2063 dev_err(svsp->dev, "node name cannot be null\n");
2064 return ERR_PTR(-EINVAL);
2065 }
2066
2067 dev = svs_get_subsys_device(svsp, node_name);
2068 if (IS_ERR(dev))
2069 return dev;
2070
2071 sup_link = device_link_add(svsp->dev, dev,
2072 DL_FLAG_AUTOREMOVE_CONSUMER);
2073 if (!sup_link) {
2074 dev_err(svsp->dev, "sup_link is NULL\n");
2075 return ERR_PTR(-EINVAL);
2076 }
2077
2078 if (sup_link->supplier->links.status != DL_DEV_DRIVER_BOUND)
2079 return ERR_PTR(-EPROBE_DEFER);
2080
2081 return dev;
2082 }
2083
svs_mt8192_platform_probe(struct svs_platform * svsp)2084 static int svs_mt8192_platform_probe(struct svs_platform *svsp)
2085 {
2086 struct device *dev;
2087 struct svs_bank *svsb;
2088 u32 idx;
2089
2090 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
2091 if (IS_ERR(svsp->rst))
2092 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
2093 "cannot get svs reset control\n");
2094
2095 dev = svs_add_device_link(svsp, "lvts");
2096 if (IS_ERR(dev))
2097 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2098 "failed to get lvts device\n");
2099
2100 for (idx = 0; idx < svsp->bank_max; idx++) {
2101 svsb = &svsp->banks[idx];
2102
2103 if (svsb->type == SVSB_HIGH)
2104 svsb->opp_dev = svs_add_device_link(svsp, "mali");
2105 else if (svsb->type == SVSB_LOW)
2106 svsb->opp_dev = svs_get_subsys_device(svsp, "mali");
2107
2108 if (IS_ERR(svsb->opp_dev))
2109 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2110 "failed to get OPP device for bank %d\n",
2111 idx);
2112 }
2113
2114 return 0;
2115 }
2116
svs_mt8183_platform_probe(struct svs_platform * svsp)2117 static int svs_mt8183_platform_probe(struct svs_platform *svsp)
2118 {
2119 struct device *dev;
2120 struct svs_bank *svsb;
2121 u32 idx;
2122
2123 dev = svs_add_device_link(svsp, "thermal");
2124 if (IS_ERR(dev))
2125 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2126 "failed to get thermal device\n");
2127
2128 for (idx = 0; idx < svsp->bank_max; idx++) {
2129 svsb = &svsp->banks[idx];
2130
2131 switch (svsb->sw_id) {
2132 case SVSB_CPU_LITTLE:
2133 case SVSB_CPU_BIG:
2134 svsb->opp_dev = get_cpu_device(svsb->cpu_id);
2135 break;
2136 case SVSB_CCI:
2137 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2138 break;
2139 case SVSB_GPU:
2140 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2141 break;
2142 default:
2143 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
2144 return -EINVAL;
2145 }
2146
2147 if (IS_ERR(svsb->opp_dev))
2148 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2149 "failed to get OPP device for bank %d\n",
2150 idx);
2151 }
2152
2153 return 0;
2154 }
2155
2156 static struct svs_bank svs_mt8192_banks[] = {
2157 {
2158 .sw_id = SVSB_GPU,
2159 .type = SVSB_LOW,
2160 .set_freq_pct = svs_set_bank_freq_pct_v3,
2161 .get_volts = svs_get_bank_volts_v3,
2162 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT,
2163 .mode_support = SVSB_MODE_INIT02,
2164 .opp_count = MAX_OPP_ENTRIES,
2165 .freq_base = 688000000,
2166 .turn_freq_base = 688000000,
2167 .volt_step = 6250,
2168 .volt_base = 400000,
2169 .vmax = 0x60,
2170 .vmin = 0x1a,
2171 .age_config = 0x555555,
2172 .dc_config = 0x1,
2173 .dvt_fixed = 0x1,
2174 .vco = 0x18,
2175 .chk_shift = 0x87,
2176 .core_sel = 0x0fff0100,
2177 .int_st = BIT(0),
2178 .ctl0 = 0x00540003,
2179 },
2180 {
2181 .sw_id = SVSB_GPU,
2182 .type = SVSB_HIGH,
2183 .set_freq_pct = svs_set_bank_freq_pct_v3,
2184 .get_volts = svs_get_bank_volts_v3,
2185 .tzone_name = "gpu1",
2186 .volt_flags = SVSB_REMOVE_DVTFIXED_VOLT |
2187 SVSB_MON_VOLT_IGNORE,
2188 .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON,
2189 .opp_count = MAX_OPP_ENTRIES,
2190 .freq_base = 902000000,
2191 .turn_freq_base = 688000000,
2192 .volt_step = 6250,
2193 .volt_base = 400000,
2194 .vmax = 0x60,
2195 .vmin = 0x1a,
2196 .age_config = 0x555555,
2197 .dc_config = 0x1,
2198 .dvt_fixed = 0x6,
2199 .vco = 0x18,
2200 .chk_shift = 0x87,
2201 .core_sel = 0x0fff0101,
2202 .int_st = BIT(1),
2203 .ctl0 = 0x00540003,
2204 .tzone_htemp = 85000,
2205 .tzone_htemp_voffset = 0,
2206 .tzone_ltemp = 25000,
2207 .tzone_ltemp_voffset = 7,
2208 },
2209 };
2210
2211 static struct svs_bank svs_mt8183_banks[] = {
2212 {
2213 .sw_id = SVSB_CPU_LITTLE,
2214 .set_freq_pct = svs_set_bank_freq_pct_v2,
2215 .get_volts = svs_get_bank_volts_v2,
2216 .cpu_id = 0,
2217 .buck_name = "proc",
2218 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY,
2219 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2220 .opp_count = MAX_OPP_ENTRIES,
2221 .freq_base = 1989000000,
2222 .vboot = 0x30,
2223 .volt_step = 6250,
2224 .volt_base = 500000,
2225 .vmax = 0x64,
2226 .vmin = 0x18,
2227 .age_config = 0x555555,
2228 .dc_config = 0x555555,
2229 .dvt_fixed = 0x7,
2230 .vco = 0x10,
2231 .chk_shift = 0x77,
2232 .core_sel = 0x8fff0000,
2233 .int_st = BIT(0),
2234 .ctl0 = 0x00010001,
2235 },
2236 {
2237 .sw_id = SVSB_CPU_BIG,
2238 .set_freq_pct = svs_set_bank_freq_pct_v2,
2239 .get_volts = svs_get_bank_volts_v2,
2240 .cpu_id = 4,
2241 .buck_name = "proc",
2242 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY,
2243 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2244 .opp_count = MAX_OPP_ENTRIES,
2245 .freq_base = 1989000000,
2246 .vboot = 0x30,
2247 .volt_step = 6250,
2248 .volt_base = 500000,
2249 .vmax = 0x58,
2250 .vmin = 0x10,
2251 .age_config = 0x555555,
2252 .dc_config = 0x555555,
2253 .dvt_fixed = 0x7,
2254 .vco = 0x10,
2255 .chk_shift = 0x77,
2256 .core_sel = 0x8fff0001,
2257 .int_st = BIT(1),
2258 .ctl0 = 0x00000001,
2259 },
2260 {
2261 .sw_id = SVSB_CCI,
2262 .set_freq_pct = svs_set_bank_freq_pct_v2,
2263 .get_volts = svs_get_bank_volts_v2,
2264 .buck_name = "proc",
2265 .volt_flags = SVSB_INIT01_VOLT_INC_ONLY,
2266 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02,
2267 .opp_count = MAX_OPP_ENTRIES,
2268 .freq_base = 1196000000,
2269 .vboot = 0x30,
2270 .volt_step = 6250,
2271 .volt_base = 500000,
2272 .vmax = 0x64,
2273 .vmin = 0x18,
2274 .age_config = 0x555555,
2275 .dc_config = 0x555555,
2276 .dvt_fixed = 0x7,
2277 .vco = 0x10,
2278 .chk_shift = 0x77,
2279 .core_sel = 0x8fff0002,
2280 .int_st = BIT(2),
2281 .ctl0 = 0x00100003,
2282 },
2283 {
2284 .sw_id = SVSB_GPU,
2285 .set_freq_pct = svs_set_bank_freq_pct_v2,
2286 .get_volts = svs_get_bank_volts_v2,
2287 .buck_name = "mali",
2288 .tzone_name = "tzts2",
2289 .volt_flags = SVSB_INIT01_PD_REQ |
2290 SVSB_INIT01_VOLT_INC_ONLY,
2291 .mode_support = SVSB_MODE_INIT01 | SVSB_MODE_INIT02 |
2292 SVSB_MODE_MON,
2293 .opp_count = MAX_OPP_ENTRIES,
2294 .freq_base = 900000000,
2295 .vboot = 0x30,
2296 .volt_step = 6250,
2297 .volt_base = 500000,
2298 .vmax = 0x40,
2299 .vmin = 0x14,
2300 .age_config = 0x555555,
2301 .dc_config = 0x555555,
2302 .dvt_fixed = 0x3,
2303 .vco = 0x10,
2304 .chk_shift = 0x77,
2305 .core_sel = 0x8fff0003,
2306 .int_st = BIT(3),
2307 .ctl0 = 0x00050001,
2308 .tzone_htemp = 85000,
2309 .tzone_htemp_voffset = 0,
2310 .tzone_ltemp = 25000,
2311 .tzone_ltemp_voffset = 3,
2312 },
2313 };
2314
2315 static const struct svs_platform_data svs_mt8192_platform_data = {
2316 .name = "mt8192-svs",
2317 .banks = svs_mt8192_banks,
2318 .efuse_parsing = svs_mt8192_efuse_parsing,
2319 .probe = svs_mt8192_platform_probe,
2320 .regs = svs_regs_v2,
2321 .bank_max = ARRAY_SIZE(svs_mt8192_banks),
2322 };
2323
2324 static const struct svs_platform_data svs_mt8183_platform_data = {
2325 .name = "mt8183-svs",
2326 .banks = svs_mt8183_banks,
2327 .efuse_parsing = svs_mt8183_efuse_parsing,
2328 .probe = svs_mt8183_platform_probe,
2329 .regs = svs_regs_v2,
2330 .bank_max = ARRAY_SIZE(svs_mt8183_banks),
2331 };
2332
2333 static const struct of_device_id svs_of_match[] = {
2334 {
2335 .compatible = "mediatek,mt8192-svs",
2336 .data = &svs_mt8192_platform_data,
2337 }, {
2338 .compatible = "mediatek,mt8183-svs",
2339 .data = &svs_mt8183_platform_data,
2340 }, {
2341 /* Sentinel */
2342 },
2343 };
2344 MODULE_DEVICE_TABLE(of, svs_of_match);
2345
svs_probe(struct platform_device * pdev)2346 static int svs_probe(struct platform_device *pdev)
2347 {
2348 struct svs_platform *svsp;
2349 const struct svs_platform_data *svsp_data;
2350 int ret, svsp_irq;
2351
2352 svsp_data = of_device_get_match_data(&pdev->dev);
2353
2354 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
2355 if (!svsp)
2356 return -ENOMEM;
2357
2358 svsp->dev = &pdev->dev;
2359 svsp->banks = svsp_data->banks;
2360 svsp->regs = svsp_data->regs;
2361 svsp->bank_max = svsp_data->bank_max;
2362
2363 ret = svsp_data->probe(svsp);
2364 if (ret)
2365 return ret;
2366
2367 if (!svs_is_efuse_data_correct(svsp)) {
2368 dev_notice(svsp->dev, "efuse data isn't correct\n");
2369 ret = -EPERM;
2370 goto svs_probe_free_efuse;
2371 }
2372
2373 if (!svsp_data->efuse_parsing(svsp)) {
2374 dev_err(svsp->dev, "efuse data parsing failed\n");
2375 ret = -EPERM;
2376 goto svs_probe_free_resource;
2377 }
2378
2379 ret = svs_bank_resource_setup(svsp);
2380 if (ret) {
2381 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret);
2382 goto svs_probe_free_resource;
2383 }
2384
2385 svsp_irq = platform_get_irq(pdev, 0);
2386 if (svsp_irq < 0) {
2387 ret = svsp_irq;
2388 goto svs_probe_free_resource;
2389 }
2390
2391 svsp->main_clk = devm_clk_get(svsp->dev, "main");
2392 if (IS_ERR(svsp->main_clk)) {
2393 dev_err(svsp->dev, "failed to get clock: %ld\n",
2394 PTR_ERR(svsp->main_clk));
2395 ret = PTR_ERR(svsp->main_clk);
2396 goto svs_probe_free_resource;
2397 }
2398
2399 ret = clk_prepare_enable(svsp->main_clk);
2400 if (ret) {
2401 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret);
2402 goto svs_probe_free_resource;
2403 }
2404
2405 svsp->base = of_iomap(svsp->dev->of_node, 0);
2406 if (IS_ERR_OR_NULL(svsp->base)) {
2407 dev_err(svsp->dev, "cannot find svs register base\n");
2408 ret = -EINVAL;
2409 goto svs_probe_clk_disable;
2410 }
2411
2412 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
2413 IRQF_ONESHOT, svsp_data->name, svsp);
2414 if (ret) {
2415 dev_err(svsp->dev, "register irq(%d) failed: %d\n",
2416 svsp_irq, ret);
2417 goto svs_probe_iounmap;
2418 }
2419
2420 ret = svs_start(svsp);
2421 if (ret) {
2422 dev_err(svsp->dev, "svs start fail: %d\n", ret);
2423 goto svs_probe_iounmap;
2424 }
2425
2426 #ifdef CONFIG_DEBUG_FS
2427 ret = svs_create_debug_cmds(svsp);
2428 if (ret) {
2429 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret);
2430 goto svs_probe_iounmap;
2431 }
2432 #endif
2433
2434 return 0;
2435
2436 svs_probe_iounmap:
2437 iounmap(svsp->base);
2438
2439 svs_probe_clk_disable:
2440 clk_disable_unprepare(svsp->main_clk);
2441
2442 svs_probe_free_resource:
2443 if (!IS_ERR_OR_NULL(svsp->tefuse))
2444 kfree(svsp->tefuse);
2445
2446 svs_probe_free_efuse:
2447 if (!IS_ERR_OR_NULL(svsp->efuse))
2448 kfree(svsp->efuse);
2449
2450 return ret;
2451 }
2452
2453 static DEFINE_SIMPLE_DEV_PM_OPS(svs_pm_ops, svs_suspend, svs_resume);
2454
2455 static struct platform_driver svs_driver = {
2456 .probe = svs_probe,
2457 .driver = {
2458 .name = "mtk-svs",
2459 .pm = &svs_pm_ops,
2460 .of_match_table = svs_of_match,
2461 },
2462 };
2463
2464 module_platform_driver(svs_driver);
2465
2466 MODULE_AUTHOR("Roger Lu <roger.lu@mediatek.com>");
2467 MODULE_DESCRIPTION("MediaTek SVS driver");
2468 MODULE_LICENSE("GPL");
2469