1 /**
2 ******************************************************************************
3 * @file rtl8721d_adc.c
4 * @author
5 * @version V1.0.0
6 * @date 2016-05-17
7 * @brief This file provides firmware functions to manage the following
8 * functionalities of the Analog to Digital Convertor (ADC) peripheral:
9 * - Initialization and Configuration
10 * - Analog configuration
11 * - Mode configuration
12 * - Interrupts and flags management
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * This module is a confidential and proprietary property of RealTek and
18 * possession or use of this module requires written permission of RealTek.
19 *
20 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved.
21 ******************************************************************************
22 */
23
24 #include "ameba_soc.h"
25
26 /**
27 * @brief Initializes the parameters in the ADC_InitStruct with default values.
28 * @param ADC_InitStruct: pointer to a ADC_InitTypeDef structure that contains
29 * the configuration information for the ADC peripheral.
30 * @retval None
31 */
ADC_StructInit(ADC_InitTypeDef * ADC_InitStruct)32 void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
33 {
34 u8 i;
35
36 ADC_InitStruct->ADC_OpMode = ADC_SW_TRI_MODE;
37 ADC_InitStruct->ADC_ClkDiv = ADC_CLK_DIV_12;
38 ADC_InitStruct->ADC_RxThresholdLevel = 0;
39 ADC_InitStruct->ADC_DMAThresholdLevel = 7;
40 ADC_InitStruct->ADC_CvlistLen = ADC_CH_NUM - 1;
41 ADC_InitStruct->ADC_ChanInType = 0;
42 ADC_InitStruct->ADC_SpecialCh = 0xFF;
43 ADC_InitStruct->ADC_ChIDEn = DISABLE;
44
45 for(i = 0; i < ADC_InitStruct->ADC_CvlistLen + 1; i++)
46 ADC_InitStruct->ADC_Cvlist[i] = i;
47 }
48
49 /**
50 * @brief Initializes the ADC according to the specified parameters in ADC_InitStruct.
51 * @param ADC_InitStruct: pointer to a ADC_InitTypeDef structure that contains
52 * the configuration information for the ADC peripheral.
53 * @retval None
54 */
ADC_Init(ADC_InitTypeDef * ADC_InitStruct)55 void ADC_Init(ADC_InitTypeDef* ADC_InitStruct)
56 {
57 ADC_TypeDef *adc = ADC;
58 u32 value = 0;
59 u8 len, i;
60
61 assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_OpMode));
62 assert_param(IS_ADC_SAMPLE_CLK(ADC_InitStruct->ADC_ClkDiv));
63 assert_param(ADC_InitStruct->ADC_CvlistLen < 16);
64
65 /* Disable ADC, clear pending interrupt, clear FIFO */
66 ADC_Cmd(DISABLE);
67
68 adc->ADC_INTR_CTRL= 0;
69 ADC_INTClear();
70 ADC_ClearFIFO();
71
72 /* Set clock divider */
73 adc->ADC_CLK_DIV = (u32)ADC_InitStruct->ADC_ClkDiv & BIT_MASK_CLK_DIV;
74
75 /* Set adc configuration*/
76 value = adc->ADC_CONF & (~(BIT_MASK_CVLIST_LEN | BIT_MASK_OP_MODE));
77 value |= (ADC_InitStruct->ADC_OpMode << BIT_SHIFT_OP_MODE) | \
78 (ADC_InitStruct->ADC_CvlistLen << BIT_SHIFT_CVLIST_LEN);
79 adc->ADC_CONF = value;
80
81 /* Set channel input type */
82 adc->ADC_IN_TYPE = ADC_InitStruct->ADC_ChanInType;
83
84 /* Set channel switch list */
85 value = 0;
86 len = ((ADC_InitStruct->ADC_CvlistLen + 1) > 8) ? 8 : (ADC_InitStruct->ADC_CvlistLen + 1);
87 for(i = 0; i < len; i++) {
88 value |= (u32)(ADC_InitStruct->ADC_Cvlist[i] << BIT_SHIFT_CHSW0(i));
89 }
90 adc->ADC_CHSW_LIST[0] = value;
91
92 value = 0;
93 if((ADC_InitStruct->ADC_CvlistLen + 1) > 8) {
94 for(i = 8; i < (ADC_InitStruct->ADC_CvlistLen + 1); i++)
95 value |= (u32)(ADC_InitStruct->ADC_Cvlist[i] << BIT_SHIFT_CHSW1(i));
96 }
97 adc->ADC_CHSW_LIST[1] = value;
98
99 /* Set particular channel */
100 if(ADC_InitStruct->ADC_SpecialCh < ADC_CH_NUM) {
101 ADC_INTConfig(BIT_ADC_IT_CHCV_END_EN, ENABLE);
102 adc->ADC_IT_CHNO_CON = (u32)ADC_InitStruct->ADC_SpecialCh;
103 }
104
105 /* Set FIFO full level */
106 adc->ADC_FULL_LVL = (u32)ADC_InitStruct->ADC_RxThresholdLevel;
107
108 /* Set DMA level */
109 value = adc->ADC_DMA_CON & (~BIT_MASK_DMA_LVL);
110 value |= (ADC_InitStruct->ADC_DMAThresholdLevel << BIT_SHIFT_DMA_LVL);
111 adc->ADC_DMA_CON = value;
112
113 /* Set channel ID included in data or not */
114 if(ADC_InitStruct->ADC_ChIDEn)
115 adc->ADC_DELAY_CNT |= BIT_ADC_DAT_CHID;
116 }
117
118 /**
119 * @brief Enable or Disable the ADC peripheral.
120 * @param NewState: new state of the ADC peripheral.
121 * This parameter can be: ENABLE or DISABLE.
122 * @retval None
123 */
ADC_Cmd(u32 NewState)124 void ADC_Cmd(u32 NewState)
125 {
126 ADC_TypeDef *adc = ADC;
127
128 if(NewState != DISABLE)
129 adc->ADC_CONF |= BIT_ADC_ENABLE;
130 else {
131 adc->ADC_CONF &= ~BIT_ADC_ENABLE;
132
133 /* Need to clear FIFO, or there will be waste data in FIFO next time ADC is enable. Ameba-D A-cut bug */
134 ADC_ClearFIFO();
135 }
136 }
137
138 /**
139 * @brief ENABLE/DISABLE the ADC interrupt bits.
140 * @param ADC_IT: specifies the ADC interrupt to be setup.
141 * This parameter can be one or combinations of the following values:
142 * @arg BIT_ADC_IT_COMP_CH10_EN: ADC channel 10 compare interrupt
143 * @arg BIT_ADC_IT_COMP_CH9_EN: ADC channel 9 compare interrupt
144 * @arg BIT_ADC_IT_COMP_CH8_EN: ADC channel 8 compare interrupt
145 * @arg BIT_ADC_IT_COMP_CH7_EN: ADC channel 7 compare interrupt
146 * @arg BIT_ADC_IT_COMP_CH6_EN: ADC channel 6 compare interrupt
147 * @arg BIT_ADC_IT_COMP_CH5_EN: ADC channel 5 compare interrupt
148 * @arg BIT_ADC_IT_COMP_CH4_EN: ADC channel 4 compare interrupt
149 * @arg BIT_ADC_IT_COMP_CH3_EN: ADC channel 3 compare interrupt
150 * @arg BIT_ADC_IT_COMP_CH2_EN: ADC channel 2 compare interrupt
151 * @arg BIT_ADC_IT_COMP_CH1_EN: ADC channel 1 compare interrupt
152 * @arg BIT_ADC_IT_COMP_CH0_EN: ADC channel 0 compare interrupt
153 * @arg BIT_ADC_IT_ERR_EN: ADC error state interrupt
154 * @arg BIT_ADC_IT_DAT_OVW_EN: ADC data overwritten interrupt
155 * @arg BIT_ADC_IT_FIFO_EMPTY_EN: ADC FIFO empty interrupt
156 * @arg BIT_ADC_IT_FIFO_OVER_EN: ADC FIFO overflow interrupt
157 * @arg BIT_ADC_IT_FIFO_FULL_EN: ADC FIFO full interrupt
158 * @arg BIT_ADC_IT_CHCV_END_EN: ADC particular channel conversion done interrupt
159 * @arg BIT_ADC_IT_CV_END_EN: ADC conversion end interrupt
160 * @arg BIT_ADC_IT_CVLIST_END_EN: ADC conversion list end interrupt
161 * @param NewState: ENABLE/DISABLE.
162 * @retval None
163 */
ADC_INTConfig(u32 ADC_IT,u32 NewState)164 void ADC_INTConfig(u32 ADC_IT, u32 NewState)
165 {
166 ADC_TypeDef *adc = ADC;
167
168 if(NewState != DISABLE) {
169 adc->ADC_INTR_CTRL |= ADC_IT;
170 } else {
171 adc->ADC_INTR_CTRL &= ~ADC_IT;
172 }
173 }
174
175 /**
176 * @brief Clears all the ADC interrupt pending bits.
177 * @param None
178 * @retval None
179 * @note This function can also used to clear raw status.
180 */
ADC_INTClear(void)181 void ADC_INTClear(void)
182 {
183 ADC_TypeDef *adc = ADC;
184
185 /* Clear the all IT pending Bits */
186 adc->ADC_INTR_STS = BIT_ADC_IT_ALL_STS;
187 }
188
189 /**
190 * @brief Clears the ADC interrupt pending bits.
191 * @param ADC_IT: specifies the pending bit to clear.
192 * This parameter can be any combination of the following values:
193 * @arg BIT_ADC_IT_COMP_CH10_STS
194 * @arg BIT_ADC_IT_COMP_CH9_STS
195 * @arg BIT_ADC_IT_COMP_CH8_STS
196 * @arg BIT_ADC_IT_COMP_CH7_STS
197 * @arg BIT_ADC_IT_COMP_CH6_STS
198 * @arg BIT_ADC_IT_COMP_CH5_STS
199 * @arg BIT_ADC_IT_COMP_CH4_STS
200 * @arg BIT_ADC_IT_COMP_CH3_STS
201 * @arg BIT_ADC_IT_COMP_CH2_STS
202 * @arg BIT_ADC_IT_COMP_CH1_STS
203 * @arg BIT_ADC_IT_COMP_CH0_STS
204 * @arg BIT_ADC_IT_ERR_STS
205 * @arg BIT_ADC_IT_DAT_OVW_STS
206 * @arg BIT_ADC_IT_FIFO_EMPTY_STS
207 * @arg BIT_ADC_IT_FIFO_OVER_STS
208 * @arg BIT_ADC_IT_FIFO_FULL_STS
209 * @arg BIT_ADC_IT_CHCV_END_STS
210 * @arg BIT_ADC_IT_CV_END_STS
211 * @arg BIT_ADC_IT_CVLIST_END_STS
212 * @retval None
213 */
ADC_INTClearPendingBits(u32 ADC_IT)214 void ADC_INTClearPendingBits(u32 ADC_IT)
215 {
216 ADC_TypeDef *adc = ADC;
217
218 adc->ADC_INTR_STS = ADC_IT;
219 }
220
221 /**
222 * @brief Get ADC interrupt status.
223 * @param None
224 * @retval Current Interrupt Status, each bit of this value represents one
225 * interrupt status which is as follows:
226 * @arg BIT_ADC_IT_COMP_CH10_STS
227 * @arg BIT_ADC_IT_COMP_CH9_STS
228 * @arg BIT_ADC_IT_COMP_CH8_STS
229 * @arg BIT_ADC_IT_COMP_CH7_STS
230 * @arg BIT_ADC_IT_COMP_CH6_STS
231 * @arg BIT_ADC_IT_COMP_CH5_STS
232 * @arg BIT_ADC_IT_COMP_CH4_STS
233 * @arg BIT_ADC_IT_COMP_CH3_STS
234 * @arg BIT_ADC_IT_COMP_CH2_STS
235 * @arg BIT_ADC_IT_COMP_CH1_STS
236 * @arg BIT_ADC_IT_COMP_CH0_STS
237 * @arg BIT_ADC_IT_ERR_STS
238 * @arg BIT_ADC_IT_DAT_OVW_STS
239 * @arg BIT_ADC_IT_FIFO_EMPTY_STS
240 * @arg BIT_ADC_IT_FIFO_OVER_STS
241 * @arg BIT_ADC_IT_FIFO_FULL_STS
242 * @arg BIT_ADC_IT_CHCV_END_STS
243 * @arg BIT_ADC_IT_CV_END_STS
244 * @arg BIT_ADC_IT_CVLIST_END_STS
245 */
ADC_GetISR(void)246 u32 ADC_GetISR(void)
247 {
248 ADC_TypeDef *adc = ADC;
249
250 return adc->ADC_INTR_STS;
251 }
252
253 /**
254 * @brief Get ADC raw interrupt status.
255 * @param None
256 * @retval Current Raw Interrupt Status, each bit of this value represents one
257 * raw interrupt status which is as follows:
258 * @arg BIT_ADC_IT_COMP_CH10_RAW_STS
259 * @arg BIT_ADC_IT_COMP_CH9_RAW_STS
260 * @arg BIT_ADC_IT_COMP_CH8_RAW_STS
261 * @arg BIT_ADC_IT_COMP_CH7_RAW_STS
262 * @arg BIT_ADC_IT_COMP_CH6_RAW_STS
263 * @arg BIT_ADC_IT_COMP_CH5_RAW_STS
264 * @arg BIT_ADC_IT_COMP_CH4_RAW_STS
265 * @arg BIT_ADC_IT_COMP_CH3_RAW_STS
266 * @arg BIT_ADC_IT_COMP_CH2_RAW_STS
267 * @arg BIT_ADC_IT_COMP_CH1_RAW_STS
268 * @arg BIT_ADC_IT_COMP_CH0_RAW_STS
269 * @arg BIT_ADC_IT_ERR_RAW_STS
270 * @arg BIT_ADC_IT_DAT_OVW_RAW_STS
271 * @arg BIT_ADC_IT_FIFO_EMPTY_RAW_STS
272 * @arg BIT_ADC_IT_FIFO_OVER_RAW_STS
273 * @arg BIT_ADC_IT_FIFO_FULL_RAW_STS
274 * @arg BIT_ADC_IT_CHCV_END_RAW_STS
275 * @arg BIT_ADC_IT_CV_END_RAW_STS
276 * @arg BIT_ADC_IT_CVLIST_END_RAW_STS
277 */
ADC_GetRawISR(void)278 u32 ADC_GetRawISR(void)
279 {
280 ADC_TypeDef *adc = ADC;
281
282 return adc->ADC_INTR_RAW_STS;
283 }
284
285 /**
286 * @brief Get the number of valid entries in ADC receive FIFO.
287 * @param None.
288 * @retval The number of valid entries in receive FIFO.
289 */
ADC_GetRxCount(void)290 u32 ADC_GetRxCount(void)
291 {
292 ADC_TypeDef *adc = ADC;
293
294 return adc->ADC_FLR & BIT_MASK_FLR;
295 }
296
297 /**
298 * @brief Get the last ADC used channel.
299 * @param None.
300 * @retval The last ADC used channel index.
301 */
ADC_GetLastChan(void)302 u32 ADC_GetLastChan(void)
303 {
304 ADC_TypeDef *adc = ADC;
305
306 return adc->ADC_LAST_CH;
307 }
308
309 /**
310 * @brief Get comparison result of ADC channel.
311 * @param ADC_Channel: The channel index
312 * @retval The comparison result of specified ADC channel.
313 */
ADC_GetCompStatus(u8 ADC_Channel)314 u32 ADC_GetCompStatus(u8 ADC_Channel)
315 {
316 ADC_TypeDef *adc = ADC;
317 u32 value = (adc->ADC_COMP_STS & BIT_MASK_COMP_STS_CH(ADC_Channel)) \
318 >> BIT_SHIFT_COMP_STS_CH(ADC_Channel);
319
320 return value;
321 }
322
323 /**
324 * @brief Set ADC channel threshold and criteria for comparison.
325 * @param ADC_channel: can be a value of @ref ADC_Chn_Selection as following:
326 * @arg ADC_CH0
327 * @arg ADC_CH1
328 * @arg ADC_CH2
329 * @arg ADC_CH3
330 * @arg ADC_CH4
331 * @arg ADC_CH5
332 * @arg ADC_CH6
333 * @arg ADC_CH7
334 * @arg ADC_CH8
335 * @arg ADC_CH9
336 * @arg ADC_CH10
337 * @param CompThresH: the higher threshold of channel for ADC automatic comparison
338 * @param CompThresH: the lower threshold of channel for ADC automatic comparison
339 * @param CompCtrl: This parameter can be a value of @ref ADC_Compare_Control_Definitions as following:
340 * @arg ADC_COMP_SMALLER_THAN_THL: less than the lower threshold
341 * @arg ADC_COMP_GREATER_THAN_THH: greater than the higher threshod
342 * @arg ADC_COMP_WITHIN_THL_AND_THH: between the lower and higher threshod
343 * @arg ADC_COMP_OUTSIDE_THL_AND_THH: out the range of the higher and lower threshod
344 * @retval None
345 */
ADC_SetComp(u8 ADC_channel,u16 CompThresH,u16 CompThresL,u8 CompCtrl)346 void ADC_SetComp(u8 ADC_channel, u16 CompThresH, u16 CompThresL, u8 CompCtrl)
347 {
348 ADC_TypeDef *adc = ADC;
349 u32 value;
350
351 assert_param(IS_ADC_CHN_SEL(ADC_channel));
352 assert_param(IS_ADC_VALID_COMP_TH(CompThresH));
353 assert_param(IS_ADC_VALID_COMP_TH(CompThresL));
354 assert_param(IS_ADC_COMP_CRITERIA(CompCtrl));
355
356 /* Set ADC channel threshold for comparison */
357 adc->ADC_COMP_TH_CH[ADC_channel] =
358 (u32)(CompThresH << BIT_SHIFT_COMP_TH_H) | (CompThresL << BIT_SHIFT_COMP_TH_L);
359
360 /* Set ADC channel comparison criteria */
361 value = adc->ADC_COMP_CTRL;
362 value &= ~ BIT_MASK_COMP_CTRL_CH(ADC_channel);
363 value |= (CompCtrl << BIT_SHIFT_COMP_CTRL_CH(ADC_channel));
364 adc->ADC_COMP_CTRL = value;
365
366 /* Enable comparison interrupt */
367 ADC_INTConfig(BIT_ADC_IT_COMP_CH_EN(ADC_channel), ENABLE);
368 }
369
370 /**
371 * @brief Reset the channel switch to default state.
372 * @param None
373 * @retval None
374 */
ADC_ResetCSwList(void)375 void ADC_ResetCSwList(void)
376 {
377 ADC_TypeDef *adc = ADC;
378
379 adc->ADC_RST_LIST = BIT_ADC_RST_LIST;
380 adc->ADC_RST_LIST = 0;
381 }
382
383 /**
384 * @brief Detemine ADC FIFO is empty or not.
385 * @param None.
386 * @retval ADC FIFO is empty or not:
387 * - 0: Not Empty
388 * - 1: Empty
389 */
ADC_Readable(void)390 u32 ADC_Readable(void)
391 {
392 u32 Status = ADC_GetStatus();
393 u32 Readable = (((Status & BIT_ADC_FIFO_EMPTY) == 0) ? 1 : 0);
394
395 return Readable;
396 }
397
398 /**
399 * @brief Read data from ADC receive FIFO .
400 * @param None
401 * @retval The conversion data.
402 */
ADC_Read(void)403 u16 ADC_Read(void)
404 {
405 u16 value = (u16)(ADC->ADC_DATA_GLOBAL & (BIT_MASK_DAT_GLOBAL | BIT_MASK_DAT_CHID));
406
407 return value;
408 }
409
410 /**
411 * @brief Continuous Read data in auto mode.
412 * @param pBuf: pointer to buffer to keep sample data
413 * @param len: the number of sample data to be read
414 * @retval None.
415 */
ADC_ReceiveBuf(u16 * pBuf,u32 len)416 void ADC_ReceiveBuf(u16 *pBuf, u32 len)
417 {
418 u32 i = 0;
419
420 ADC_AutoCSwCmd(ENABLE);
421
422 for(i = 0; i < len; i++){
423 while(ADC_Readable() == 0);
424 pBuf[i] = ADC_Read();
425 }
426 ADC_AutoCSwCmd(DISABLE);
427 }
428
429 /**
430 * @brief Clear ADC FIFO.
431 * @param None
432 * @retval None
433 */
ADC_ClearFIFO(void)434 void ADC_ClearFIFO(void)
435 {
436 ADC->ADC_CLR_FIFO = 1;
437 ADC->ADC_CLR_FIFO = 0;
438 }
439
440 /**
441 * @brief Get ADC status.
442 * @param None
443 * @retval Current status,each bit of this value represents one status which is as follows:
444 *
445 * bit 2 : BIT_ADC_FIFO_EMPTY ADC FIFO Empty.
446 * - 0: FIFO in ADC is not empty
447 * - 1: FIFO in ADC is empty
448 *
449 * bit 1 : BIT_ADC_FIFO_FULL_REAL ADC FIFO real full flag.
450 * - 0: FIFO in ADC is not full real
451 * - 1: FIFO in ADC is full real
452 *
453 * bit 0 : BIT_ADC_BUSY_STS ADC busy Flag.
454 * - 0: The ADC is ready
455 * - 1: The ADC is busy
456 */
ADC_GetStatus(void)457 u32 ADC_GetStatus(void)
458 {
459 ADC_TypeDef *adc = ADC;
460
461 return adc->ADC_BUSY_STS;
462 }
463
464 /**
465 * @brief Control the ADC module to do a conversion. Used as a start-convert event which is controlled by software.
466 * @param NewState: can be one of the following value:
467 * @arg ENABLE: Enable the analog module and analog mux. And then start a new channel conversion.
468 * @arg DISABLE: Disable the analog module and analog mux.
469 * @retval None.
470 * @note 1. Every time this bit is set to 1, ADC module would switch to a new channel and do one conversion.
471 * Every time a conversion is done, software MUST clear this bit manually.
472 * 2. Used in Sotfware Trigger Mode
473 */
ADC_SWTrigCmd(u32 NewState)474 void ADC_SWTrigCmd(u32 NewState)
475 {
476 ADC_TypeDef *adc = ADC;
477 u8 div = adc->ADC_CLK_DIV;
478 u8 sync_time[4] = {12, 16, 32, 64};
479
480 if(NewState != DISABLE)
481 adc->ADC_SW_TRIG = BIT_ADC_SW_TRIG;
482 else
483 adc->ADC_SW_TRIG = 0;
484
485 /* Wait 2 clock to sync signal */
486 DelayUs(sync_time[div]);
487 }
488
489 /**
490 * @brief Controls the automatic channel switch enabled or disabled.
491 * @param NewState: can be one of the following value:
492 * @arg ENABLE: Enable the automatic channel switch.
493 * When setting this bit, an automatic channel switch starts from the first channel in the channel switch list.
494 * @arg DISABLE: Disable the automatic channel switch.
495 * If an automatic channel switch is in progess, writing 0 will terminate the automatic channel switch.
496 * @retval None.
497 * @note Used in Automatic Mode
498 */
ADC_AutoCSwCmd(u32 NewState)499 void ADC_AutoCSwCmd(u32 NewState)
500 {
501 ADC_TypeDef *adc = ADC;
502 u8 div = adc->ADC_CLK_DIV;
503 u8 sync_time[4] = {12, 16, 32, 64};
504
505 if(NewState != DISABLE)
506 adc->ADC_AUTO_CSW_CTRL = BIT_ADC_AUTO_CSW_EN;
507 else
508 adc->ADC_AUTO_CSW_CTRL = 0;
509
510 /* Wait 2 clock to sync signal */
511 DelayUs(sync_time[div]);
512 }
513
514 /**
515 * @brief Initialize the trigger timer when in ADC Timer-Trigger Mode.
516 * @param Tim_Idx: The timer index would be used to make ADC module do a conversion.
517 * @param PeriodMs: Indicate the period of trigger timer.
518 * @param NewState: can be one of the following value:
519 * @arg ENABLE: Enable the ADC timer trigger mode.
520 * @arg DISABLE: Disable the ADC timer trigger mode.
521 * @retval None.
522 * @note Used in Timer-Trigger Mode
523 */
ADC_TimerTrigCmd(u8 Tim_Idx,u32 PeriodMs,u32 NewState)524 void ADC_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState)
525 {
526 ADC_TypeDef *adc = ADC;
527 RTIM_TimeBaseInitTypeDef TIM_InitStruct;
528
529 assert_param(IS_ADC_VALID_TIM(Tim_Idx));
530
531 adc->ADC_EXT_TRIG_TIMER_SEL = Tim_Idx;
532
533 if(NewState != DISABLE) {
534 RTIM_TimeBaseStructInit(&TIM_InitStruct);
535 TIM_InitStruct.TIM_Idx = Tim_Idx;
536 TIM_InitStruct.TIM_Period = (PeriodMs *32768)/1000/2;//ms to tick
537
538 RTIM_TimeBaseInit(TIMx_LP[Tim_Idx], &TIM_InitStruct, TIMx_irq_LP[Tim_Idx], (IRQ_FUN)NULL, (u32)NULL);
539 RTIM_Cmd(TIMx_LP[Tim_Idx], ENABLE);
540 } else {
541 RTIM_Cmd(TIMx_LP[Tim_Idx], DISABLE);
542 }
543 }
544
545 /**
546 * @brief Enable or Disable DMA read mode.
547 * @param newState: ENABLE/DISABLE
548 * @retval None.
549 */
ADC_SetDmaEnable(u32 newState)550 void ADC_SetDmaEnable(u32 newState)
551 {
552 if (newState == DISABLE)
553 ADC->ADC_DMA_CON &= ~BIT_ADC_DMA_EN;
554 else
555 ADC->ADC_DMA_CON |= BIT_ADC_DMA_EN;
556 }
557
558 /**
559 * @brief Init and Enable ADC RX GDMA.
560 * @param GDMA_InitStruct: pointer to a GDMA_InitTypeDef structure that contains
561 * the configuration information for the GDMA peripheral.
562 * @param CallbackData: GDMA callback data.
563 * @param CallbackFunc: GDMA callback function.
564 * @param pDataBuf: Rx Buffer.
565 * @param DataLen: Rx Count.
566 * @retval TRUE/FLASE
567 */
ADC_RXGDMA_Init(GDMA_InitTypeDef * GDMA_InitStruct,void * CallbackData,IRQ_FUN CallbackFunc,u8 * pDataBuf,u32 DataLen)568 u32 ADC_RXGDMA_Init(
569 GDMA_InitTypeDef *GDMA_InitStruct,
570 void *CallbackData,
571 IRQ_FUN CallbackFunc,
572 u8* pDataBuf,
573 u32 DataLen)
574 {
575 u8 GdmaChnl;
576
577 GdmaChnl = GDMA_ChnlAlloc(0, (IRQ_FUN)CallbackFunc, (u32)CallbackData, 12);
578 if (GdmaChnl == 0xFF) {
579 DBG_8195A("ADC_RXGDMA_Init GDMA busy \n");
580 return _FALSE;
581 }
582
583 /* ADC RX DMA */
584 _memset((void *)GDMA_InitStruct, 0, sizeof(GDMA_InitTypeDef));
585
586 GDMA_InitStruct->MuliBlockCunt = 0;
587 GDMA_InitStruct->MaxMuliBlock = 1;//MaxLlp;
588 GDMA_InitStruct->GDMA_SrcDataWidth = TrWidthTwoBytes;
589 GDMA_InitStruct->GDMA_DstDataWidth = TrWidthTwoBytes;
590 GDMA_InitStruct->GDMA_SrcMsize = MsizeEight;
591 GDMA_InitStruct->GDMA_DstMsize = MsizeEight;
592 GDMA_InitStruct->GDMA_SrcInc = NoChange;
593 GDMA_InitStruct->GDMA_DstInc = IncType;
594 GDMA_InitStruct->GDMA_DIR = TTFCPeriToMem;
595 GDMA_InitStruct->GDMA_SrcHandshakeInterface = GDMA_HANDSHAKE_INTERFACE_ADC_RX;
596 GDMA_InitStruct->GDMA_ReloadSrc = 1;
597 GDMA_InitStruct->GDMA_IsrType = (BlockType|TransferType|ErrType);
598 GDMA_InitStruct->GDMA_ChNum = GdmaChnl;
599 GDMA_InitStruct->GDMA_Index = 0;
600
601 GDMA_InitStruct->GDMA_BlockSize = DataLen;
602 GDMA_InitStruct->GDMA_SrcAddr = (u32)&(ADC->ADC_DATA_GLOBAL);
603 GDMA_InitStruct->GDMA_DstAddr = (u32)pDataBuf;
604
605 /* GDMA initialization */
606 GDMA_Init(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, GDMA_InitStruct);
607 GDMA_Cmd(GDMA_InitStruct->GDMA_Index, GDMA_InitStruct->GDMA_ChNum, ENABLE);
608
609 return _TRUE;
610 }
611
612 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/
613