1 /** 2 ****************************************************************************** 3 * @file stm32f0xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file containing functions prototypes of ADC HAL library. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef __STM32F0xx_HAL_ADC_H 38 #define __STM32F0xx_HAL_ADC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Includes ------------------------------------------------------------------*/ 45 #include "stm32f0xx_hal_def.h" 46 47 /** @addtogroup STM32F0xx_HAL_Driver 48 * @{ 49 */ 50 51 /** @addtogroup ADC 52 * @{ 53 */ 54 55 /* Exported types ------------------------------------------------------------*/ 56 /** @defgroup ADC_Exported_Types ADC Exported Types 57 * @{ 58 */ 59 60 /** 61 * @brief Structure definition of ADC initialization and regular group 62 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. 63 * ADC state can be either: 64 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') 65 * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. 66 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 67 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 68 */ 69 typedef struct 70 { 71 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. 72 This parameter can be a value of @ref ADC_ClockPrescaler 73 Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. 74 Note: This parameter can be modified only if the ADC is disabled */ 75 uint32_t Resolution; /*!< Configures the ADC resolution. 76 This parameter can be a value of @ref ADC_Resolution */ 77 uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. 78 This parameter can be a value of @ref ADC_Data_align */ 79 uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. 80 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 81 Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): 82 If only 1 channel is set: Conversion is performed in single mode. 83 If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). 84 Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). 85 This parameter can be a value of @ref ADC_Scan_mode */ 86 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 87 This parameter can be a value of @ref ADC_EOCSelection. */ 88 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous 89 conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). 90 This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 91 This parameter can be set to ENABLE or DISABLE. 92 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. 93 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed 94 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ 95 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). 96 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). 97 This parameter can be set to ENABLE or DISABLE. 98 Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ 99 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 100 after the selected trigger occurred (software start or external trigger). 101 This parameter can be set to ENABLE or DISABLE. */ 102 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). 103 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 104 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 105 This parameter can be set to ENABLE or DISABLE 106 Note: Number of discontinuous ranks increment is fixed to one-by-one. */ 107 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 108 If set to ADC_SOFTWARE_START, external triggers are disabled. 109 This parameter can be a value of @ref ADC_External_trigger_source_Regular */ 110 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 111 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. 112 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ 113 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) 114 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 115 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 116 This parameter can be set to ENABLE or DISABLE. */ 117 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten 118 This parameter has an effect on regular group only, including in DMA mode. 119 This parameter can be a value of @ref ADC_Overrun */ 120 uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. 121 Unit: ADC clock cycles 122 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 123 Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. 124 This parameter can be a value of @ref ADC_sampling_times 125 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 126 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 127 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ 128 }ADC_InitTypeDef; 129 130 /** 131 * @brief Structure definition of ADC channel for regular group 132 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. 133 * ADC state can be either: 134 * - For all parameters: ADC disabled or enabled without conversion on going on regular group. 135 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 136 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 137 */ 138 typedef struct 139 { 140 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 141 This parameter can be a value of @ref ADC_channels 142 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ 143 uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. 144 On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. 145 Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. 146 This parameter can be a value of @ref ADC_rank */ 147 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 148 Unit: ADC clock cycles 149 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 150 This parameter can be a value of @ref ADC_sampling_times 151 Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. 152 Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. 153 If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. 154 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 155 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 156 Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ 157 }ADC_ChannelConfTypeDef; 158 159 /** 160 * @brief Structure definition of ADC analog watchdog 161 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 162 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. 163 */ 164 typedef struct 165 { 166 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. 167 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 168 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 169 This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. 170 This parameter can be a value of @ref ADC_channels. */ 171 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 172 This parameter can be set to ENABLE or DISABLE */ 173 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 174 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 175 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. 176 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ 177 }ADC_AnalogWDGConfTypeDef; 178 179 /** 180 * @brief HAL ADC state machine: ADC states definition (bitfields) 181 * @note ADC state machine is managed by bitfields, state must be compared 182 * with bit by bit. 183 * For example: 184 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " 185 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " 186 */ 187 /* States of ADC global scope */ 188 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ 189 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ 190 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ 191 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ 192 193 /* States of ADC errors */ 194 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ 195 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ 196 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ 197 198 /* States of ADC group regular */ 199 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, 200 external trigger, low power auto power-on, multimode ADC master control) */ 201 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ 202 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ 203 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ 204 205 /* States of ADC group injected */ 206 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, 207 external trigger, low power auto power-on, multimode ADC master control) */ 208 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ 209 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ 210 211 /* States of ADC analog watchdogs */ 212 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ 213 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ 214 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ 215 216 /* States of ADC multi-mode */ 217 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ 218 219 220 /** 221 * @brief ADC handle Structure definition 222 */ 223 typedef struct 224 { 225 ADC_TypeDef *Instance; /*!< Register base address */ 226 227 ADC_InitTypeDef Init; /*!< ADC required parameters */ 228 229 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 230 231 HAL_LockTypeDef Lock; /*!< ADC locking object */ 232 233 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 234 235 __IO uint32_t ErrorCode; /*!< ADC Error code */ 236 }ADC_HandleTypeDef; 237 /** 238 * @} 239 */ 240 241 242 243 /* Exported constants --------------------------------------------------------*/ 244 245 /** @defgroup ADC_Exported_Constants ADC Exported Constants 246 * @{ 247 */ 248 249 /** @defgroup ADC_Error_Code ADC Error Code 250 * @{ 251 */ 252 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 253 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, 254 enable/disable, erroneous state */ 255 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 256 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 257 258 /** 259 * @} 260 */ 261 262 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler 263 * @{ 264 */ 265 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ 266 267 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ 268 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ 269 270 /** 271 * @} 272 */ 273 274 /** @defgroup ADC_Resolution ADC Resolution 275 * @{ 276 */ 277 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ 278 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ 279 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ 280 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ 281 /** 282 * @} 283 */ 284 285 /** @defgroup ADC_Data_align ADC Data_align 286 * @{ 287 */ 288 #define ADC_DATAALIGN_RIGHT (0x00000000U) 289 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) 290 /** 291 * @} 292 */ 293 294 /** @defgroup ADC_Scan_mode ADC Scan mode 295 * @{ 296 */ 297 /* Note: Scan mode values must be compatible with other STM32 devices having */ 298 /* a configurable sequencer. */ 299 /* Scan direction setting values are defined by taking in account */ 300 /* already defined values for other STM32 devices: */ 301 /* ADC_SCAN_DISABLE (0x00000000U) */ 302 /* ADC_SCAN_ENABLE (0x00000001U) */ 303 /* Scan direction forward is considered as default setting equivalent */ 304 /* to scan enable. */ 305 /* Scan direction backward is considered as additional setting. */ 306 /* In case of migration from another STM32 device, the user will be */ 307 /* warned of change of setting choices with assert check. */ 308 #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ 309 #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ 310 311 #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ 312 313 /** 314 * @} 315 */ 316 317 /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular 318 * @{ 319 */ 320 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) 321 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) 322 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) 323 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) 324 /** 325 * @} 326 */ 327 328 /** @defgroup ADC_EOCSelection ADC EOCSelection 329 * @{ 330 */ 331 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) 332 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) 333 /** 334 * @} 335 */ 336 337 /** @defgroup ADC_Overrun ADC Overrun 338 * @{ 339 */ 340 #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) 341 #define ADC_OVR_DATA_PRESERVED (0x00000001U) 342 /** 343 * @} 344 */ 345 346 /** @defgroup ADC_rank ADC rank 347 * @{ 348 */ 349 #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ 350 #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ 351 /** 352 * @} 353 */ 354 355 /** @defgroup ADC_sampling_times ADC sampling times 356 * @{ 357 */ 358 /* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ 359 /* to distinguish this parameter versus reset value 0x00000000, */ 360 /* in the context of management of parameters "SamplingTimeCommon" */ 361 /* and "SamplingTime" (obsolete)). */ 362 #define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */ 363 #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ 364 #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ 365 #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ 366 #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ 367 #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ 368 #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ 369 #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ 370 /** 371 * @} 372 */ 373 374 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode 375 * @{ 376 */ 377 #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) 378 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) 379 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) 380 /** 381 * @} 382 */ 383 384 /** @defgroup ADC_Event_type ADC Event type 385 * @{ 386 */ 387 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ 388 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 389 /** 390 * @} 391 */ 392 393 /** @defgroup ADC_interrupts_definition ADC interrupts definition 394 * @{ 395 */ 396 #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ 397 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 398 #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ 399 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ 400 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ 401 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 402 /** 403 * @} 404 */ 405 406 /** @defgroup ADC_flags_definition ADC flags definition 407 * @{ 408 */ 409 #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ 410 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 411 #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ 412 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 413 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 414 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 415 /** 416 * @} 417 */ 418 419 /** 420 * @} 421 */ 422 423 424 /* Private constants ---------------------------------------------------------*/ 425 426 /** @addtogroup ADC_Private_Constants ADC Private Constants 427 * @{ 428 */ 429 430 /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular 431 * @{ 432 */ 433 434 /* List of external triggers of regular group for ADC1: */ 435 /* (used internally by HAL driver. To not use into HAL structure parameters) */ 436 #define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U) 437 #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) 438 #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) 439 #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) 440 #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) 441 /** 442 * @} 443 */ 444 445 /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ 446 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) 447 448 /** 449 * @} 450 */ 451 452 453 /* Exported macro ------------------------------------------------------------*/ 454 455 /** @defgroup ADC_Exported_Macros ADC Exported Macros 456 * @{ 457 */ 458 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 459 /* final user. */ 460 461 /** 462 * @brief Enable the ADC peripheral 463 * @param __HANDLE__ ADC handle 464 * @retval None 465 */ 466 #define __HAL_ADC_ENABLE(__HANDLE__) \ 467 ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) 468 469 /** 470 * @brief Disable the ADC peripheral 471 * @param __HANDLE__ ADC handle 472 * @retval None 473 */ 474 #define __HAL_ADC_DISABLE(__HANDLE__) \ 475 do{ \ 476 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ 477 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 478 } while(0) 479 480 /** 481 * @brief Enable the ADC end of conversion interrupt. 482 * @param __HANDLE__ ADC handle 483 * @param __INTERRUPT__ ADC Interrupt 484 * This parameter can be any combination of the following values: 485 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 486 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 487 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 488 * @arg ADC_IT_OVR: ADC overrun interrupt source 489 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 490 * @arg ADC_IT_RDY: ADC Ready interrupt source 491 * @retval None 492 */ 493 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 494 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 495 496 /** 497 * @brief Disable the ADC end of conversion interrupt. 498 * @param __HANDLE__ ADC handle 499 * @param __INTERRUPT__ ADC Interrupt 500 * This parameter can be any combination of the following values: 501 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 502 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 503 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 504 * @arg ADC_IT_OVR: ADC overrun interrupt source 505 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 506 * @arg ADC_IT_RDY: ADC Ready interrupt source 507 * @retval None 508 */ 509 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 510 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 511 512 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 513 * @param __HANDLE__ ADC handle 514 * @param __INTERRUPT__ ADC interrupt source to check 515 * This parameter can be any combination of the following values: 516 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source 517 * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source 518 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source 519 * @arg ADC_IT_OVR: ADC overrun interrupt source 520 * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source 521 * @arg ADC_IT_RDY: ADC Ready interrupt source 522 * @retval State ofinterruption (SET or RESET) 523 */ 524 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 525 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 526 527 /** 528 * @brief Get the selected ADC's flag status. 529 * @param __HANDLE__ ADC handle 530 * @param __FLAG__ ADC flag 531 * This parameter can be any combination of the following values: 532 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 533 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag 534 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 535 * @arg ADC_FLAG_OVR: ADC overrun flag 536 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag 537 * @arg ADC_FLAG_RDY: ADC Ready flag 538 * @retval None 539 */ 540 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 541 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 542 543 /** 544 * @brief Clear the ADC's pending flags 545 * @param __HANDLE__ ADC handle 546 * @param __FLAG__ ADC flag 547 * This parameter can be any combination of the following values: 548 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag 549 * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag 550 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag 551 * @arg ADC_FLAG_OVR: ADC overrun flag 552 * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag 553 * @arg ADC_FLAG_RDY: ADC Ready flag 554 * @retval None 555 */ 556 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 557 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 558 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 559 560 /** @brief Reset ADC handle state 561 * @param __HANDLE__ ADC handle 562 * @retval None 563 */ 564 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 565 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 566 567 /** 568 * @} 569 */ 570 571 572 /* Private macro -------------------------------------------------------------*/ 573 574 /** @defgroup ADC_Private_Macros ADC Private Macros 575 * @{ 576 */ 577 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 578 /* code of final user. */ 579 580 581 /** 582 * @brief Verification of hardware constraints before ADC can be enabled 583 * @param __HANDLE__ ADC handle 584 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 585 */ 586 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 587 (( ( ((__HANDLE__)->Instance->CR) & \ 588 (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ 589 ) == RESET \ 590 ) ? SET : RESET) 591 592 /** 593 * @brief Verification of hardware constraints before ADC can be disabled 594 * @param __HANDLE__ ADC handle 595 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 596 */ 597 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 598 (( ( ((__HANDLE__)->Instance->CR) & \ 599 (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 600 ) ? SET : RESET) 601 602 /** 603 * @brief Verification of ADC state: enabled or disabled 604 * @param __HANDLE__ ADC handle 605 * @retval SET (ADC enabled) or RESET (ADC disabled) 606 */ 607 /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ 608 /* performed automatically by hardware and flag ADC_FLAG_RDY is not */ 609 /* set. */ 610 #define ADC_IS_ENABLE(__HANDLE__) \ 611 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 612 (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ 613 ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ 614 ) ? SET : RESET) 615 616 /** 617 * @brief Test if conversion trigger of regular group is software start 618 * or external trigger. 619 * @param __HANDLE__ ADC handle 620 * @retval SET (software start) or RESET (external trigger) 621 */ 622 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 623 (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) 624 625 /** 626 * @brief Check if no conversion on going on regular group 627 * @param __HANDLE__ ADC handle 628 * @retval SET (conversion is on going) or RESET (no conversion is on going) 629 */ 630 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 631 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ 632 ) ? RESET : SET) 633 634 /** 635 * @brief Returns resolution bits in CFGR1 register: RES[1:0]. 636 * Returned value is among parameters to @ref ADC_Resolution. 637 * @param __HANDLE__ ADC handle 638 * @retval None 639 */ 640 #define ADC_GET_RESOLUTION(__HANDLE__) \ 641 (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) 642 643 /** 644 * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. 645 * Returned value is among parameters to @ref ADC_Resolution. 646 * @param __HANDLE__ ADC handle 647 * @retval None 648 */ 649 #define ADC_GET_SAMPLINGTIME(__HANDLE__) \ 650 (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) 651 652 /** 653 * @brief Simultaneously clears and sets specific bits of the handle State 654 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 655 * the first parameter is the ADC handle State, the second parameter is the 656 * bit field to clear, the third and last parameter is the bit field to set. 657 * @retval None 658 */ 659 #define ADC_STATE_CLR_SET MODIFY_REG 660 661 /** 662 * @brief Clear ADC error code (set it to error code: "no error") 663 * @param __HANDLE__ ADC handle 664 * @retval None 665 */ 666 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ 667 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 668 669 670 /** 671 * @brief Configure the channel number into channel selection register 672 * @param _CHANNEL_ ADC Channel 673 * @retval None 674 */ 675 /* This function converts ADC channels from numbers (see defgroup ADC_channels) 676 to bitfields, to get the equivalence of CMSIS channels: 677 ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) 678 ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) 679 ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) 680 ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) 681 ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) 682 ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) 683 ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) 684 ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) 685 ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) 686 ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) 687 ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) 688 ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) 689 ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) 690 ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) 691 ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) 692 ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) 693 ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) 694 ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) 695 ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) 696 */ 697 #define ADC_CHSELR_CHANNEL(_CHANNEL_) \ 698 ( 1U << (_CHANNEL_)) 699 700 /** 701 * @brief Set the ADC's sample time 702 * @param _SAMPLETIME_ Sample time parameter. 703 * @retval None 704 */ 705 /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ 706 /* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ 707 /* distinguish this parameter versus reset value 0x00000000, */ 708 /* in the context of management of parameters "SamplingTimeCommon" */ 709 /* and "SamplingTime" (obsolete)). */ 710 #define ADC_SMPR_SET(_SAMPLETIME_) \ 711 ((_SAMPLETIME_) & (ADC_SMPR_SMP)) 712 713 /** 714 * @brief Set the Analog Watchdog 1 channel. 715 * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. 716 * @retval None 717 */ 718 #define ADC_CFGR_AWDCH(_CHANNEL_) \ 719 ((_CHANNEL_) << 26U) 720 721 /** 722 * @brief Enable ADC discontinuous conversion mode for regular group 723 * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. 724 * @retval None 725 */ 726 #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ 727 ((_REG_DISCONTINUOUS_MODE_) << 16U) 728 729 /** 730 * @brief Enable the ADC auto off mode. 731 * @param _AUTOOFF_ Auto off bit enable or disable. 732 * @retval None 733 */ 734 #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ 735 ((_AUTOOFF_) << 15U) 736 737 /** 738 * @brief Enable the ADC auto delay mode. 739 * @param _AUTOWAIT_ Auto delay bit enable or disable. 740 * @retval None 741 */ 742 #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ 743 ((_AUTOWAIT_) << 14U) 744 745 /** 746 * @brief Enable ADC continuous conversion mode. 747 * @param _CONTINUOUS_MODE_ Continuous mode. 748 * @retval None 749 */ 750 #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ 751 ((_CONTINUOUS_MODE_) << 13U) 752 753 /** 754 * @brief Enable ADC overrun mode. 755 * @param _OVERRUN_MODE_ Overrun mode. 756 * @retval Overun bit setting to be programmed into CFGR register 757 */ 758 /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ 759 /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ 760 /* as the default case to be compliant with other STM32 devices. */ 761 #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ 762 ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ 763 )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ 764 ) 765 766 /** 767 * @brief Enable ADC scan mode to convert multiple ranks with sequencer. 768 * @param _SCAN_MODE_ Scan conversion mode. 769 * @retval None 770 */ 771 /* Note: Scan mode set using this macro (instead of parameter direct set) */ 772 /* due to different modes on other STM32 devices: to avoid any */ 773 /* unwanted setting, the exact parameter corresponding to the device */ 774 /* must be passed to this macro. */ 775 #define ADC_SCANDIR(_SCAN_MODE_) \ 776 ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ 777 )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ 778 ) 779 780 /** 781 * @brief Enable the ADC DMA continuous request. 782 * @param _DMACONTREQ_MODE_ DMA continuous request mode. 783 * @retval None 784 */ 785 #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ 786 ((_DMACONTREQ_MODE_) << 1U) 787 788 /** 789 * @brief Configure the analog watchdog high threshold into register TR. 790 * @param _Threshold_ Threshold value 791 * @retval None 792 */ 793 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ 794 ((_Threshold_) << 16U) 795 796 /** 797 * @brief Shift the AWD threshold in function of the selected ADC resolution. 798 * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 799 * If resolution 12 bits, no shift. 800 * If resolution 10 bits, shift of 2 ranks on the left. 801 * If resolution 8 bits, shift of 4 ranks on the left. 802 * If resolution 6 bits, shift of 6 ranks on the left. 803 * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) 804 * @param __HANDLE__ ADC handle 805 * @param _Threshold_ Value to be shifted 806 * @retval None 807 */ 808 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ 809 ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2)) 810 811 812 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ 813 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 814 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) 815 816 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ 817 ((RESOLUTION) == ADC_RESOLUTION_10B) || \ 818 ((RESOLUTION) == ADC_RESOLUTION_8B) || \ 819 ((RESOLUTION) == ADC_RESOLUTION_6B) ) 820 821 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ 822 ((ALIGN) == ADC_DATAALIGN_LEFT) ) 823 824 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ 825 ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) 826 827 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 828 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 829 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 830 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 831 832 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ 833 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) 834 835 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ 836 ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) 837 838 #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ 839 ((WATCHDOG) == ADC_RANK_NONE) ) 840 841 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ 842 ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ 843 ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ 844 ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ 845 ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ 846 ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ 847 ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ 848 ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) 849 850 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ 851 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 852 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) 853 854 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ 855 ((EVENT) == ADC_OVR_EVENT) ) 856 857 /** @defgroup ADC_range_verification ADC range verification 858 * in function of ADC resolution selected (12, 10, 8 or 6 bits) 859 * @{ 860 */ 861 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ 862 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ 863 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ 864 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ 865 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) 866 /** 867 * @} 868 */ 869 870 /** @defgroup ADC_regular_rank_verification ADC regular rank verification 871 * @{ 872 */ 873 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U))) 874 /** 875 * @} 876 */ 877 878 /** 879 * @} 880 */ 881 882 /* Include ADC HAL Extension module */ 883 #include "stm32f0xx_hal_adc_ex.h" 884 885 /* Exported functions --------------------------------------------------------*/ 886 /** @addtogroup ADC_Exported_Functions 887 * @{ 888 */ 889 890 /** @addtogroup ADC_Exported_Functions_Group1 891 * @{ 892 */ 893 894 895 /* Initialization and de-initialization functions **********************************/ 896 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 897 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 898 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 899 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 900 /** 901 * @} 902 */ 903 904 /* IO operation functions *****************************************************/ 905 906 /** @addtogroup ADC_Exported_Functions_Group2 907 * @{ 908 */ 909 910 911 /* Blocking mode: Polling */ 912 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 913 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 914 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 915 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 916 917 /* Non-blocking mode: Interruption */ 918 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 919 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 920 921 /* Non-blocking mode: DMA */ 922 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 923 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 924 925 /* ADC retrieve conversion value intended to be used with polling or interruption */ 926 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 927 928 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 929 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 930 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 931 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 932 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 933 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 934 /** 935 * @} 936 */ 937 938 939 /* Peripheral Control functions ***********************************************/ 940 /** @addtogroup ADC_Exported_Functions_Group3 941 * @{ 942 */ 943 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 944 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 945 /** 946 * @} 947 */ 948 949 950 /* Peripheral State functions *************************************************/ 951 /** @addtogroup ADC_Exported_Functions_Group4 952 * @{ 953 */ 954 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 955 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 956 /** 957 * @} 958 */ 959 960 961 /** 962 * @} 963 */ 964 965 966 /** 967 * @} 968 */ 969 970 /** 971 * @} 972 */ 973 974 #ifdef __cplusplus 975 } 976 #endif 977 978 979 #endif /* __STM32F0xx_HAL_ADC_H */ 980 981 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 982 983