1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *     Juno V2M System registers definitions.
9  */
10 
11 #ifndef V2M_SYS_REGS_H
12 #define V2M_SYS_REGS_H
13 
14 #include "juno_mmap.h"
15 
16 #include <fwk_macros.h>
17 
18 #include <stdint.h>
19 
20 enum v2m_sys_regs_adc_dev {
21     SYS_REGS_ADC_DEV_SYS,
22     SYS_REGS_ADC_DEV_BIG,
23     SYS_REGS_ADC_DEV_LITTLE,
24     SYS_REGS_ADC_DEV_GPU,
25     SYS_REGS_ADC_DEV_COUNT,
26 };
27 
28 struct v2m_sys_regs {
29     FWK_RW  uint32_t  ID;
30     FWK_RW  uint32_t  USERSW;
31     FWK_RW  uint32_t  LED;
32             uint32_t  RESERVED1[6];
33     FWK_RW  uint32_t  T100HZ;
34             uint32_t  RESERVED2[8];
35     FWK_RW  uint32_t  MCI;
36     FWK_RW  uint32_t  FLASH;
37             uint32_t  RESERVED3[2];
38     FWK_RW  uint32_t  CONFSW;
39             uint32_t  RESERVED4;
40     FWK_RW  uint32_t  MISC;
41             uint32_t  RESERVED5[8];
42     FWK_RW  uint32_t  PROCID0;
43     FWK_RW  uint32_t  PROCID1;
44             uint32_t  RESERVED6[5];
45     FWK_RW  uint32_t  CFG_DATA;
46     FWK_RW  uint32_t  CFG_CTRL;
47     FWK_RW  uint32_t  CFG_STAT;
48             uint32_t  RESERVED7[9];
49     FWK_R   uint32_t  ADC_CURRENT[SYS_REGS_ADC_DEV_COUNT];
50     FWK_R   uint32_t  ADC_VOLT[SYS_REGS_ADC_DEV_COUNT];
51     FWK_R   uint32_t  ADC_POWER[SYS_REGS_ADC_DEV_COUNT];
52     FWK_RW  uint64_t  ADC_ENERGY[SYS_REGS_ADC_DEV_COUNT];
53 };
54 
55 #define V2M_SYS_REGS ((struct v2m_sys_regs *) V2M_SYS_REG_BASE)
56 
57 #define V2M_SYS_REGS_ID_REV_POS   28
58 #define V2M_SYS_REGS_ID_VAR_MASK  0x000F000
59 #define V2M_SYS_REGS_ID_VAR_POS   12
60 
61 #endif /* V2M_SYS_REGS_H */
62