1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 6 #ifndef __IMX7ULP_H__ 7 #define __IMX7ULP_H__ 8 9 #include <registers/imx7ulp-crm.h> 10 11 #define GIC_BASE 0x40020000 12 #define GIC_SIZE 0x8000 13 #define GICC_OFFSET 0x2000 14 #define GICD_OFFSET 0x1000 15 16 #define AIPS0_BASE 0x40000000 17 #define AIPS0_SIZE 0x800000 18 #define AIPS1_BASE 0x40800000 19 #define AIPS1_SIZE 0x800000 20 #define M4_AIPS_BASE 0x41000000 21 #define M4_AIPS_SIZE 0x100000 22 #define M4_AIPS0_BASE 0x41000000 23 #define M4_AIPS0_SIZE 0x80000 24 #define M4_AIPS1_BASE 0x41080000 25 #define M4_AIPS1_SIZE 0x80000 26 27 #define GPIOC_BASE 0x400f0000 28 #define GPIOD_BASE 0x400f0040 29 #define GPIOE_BASE 0x400f0080 30 #define GPIOF_BASE 0x400f00c0 31 #define TPM5_BASE 0x40260000 32 #define WDOG_BASE 0x403d0000 33 #define WDOG_SIZE 0x10 34 #define SCG1_BASE 0x403e0000 35 #define PCC2_BASE 0x403f0000 36 #define PMC1_BASE 0x40400000 37 #define SMC1_BASE 0x40410000 38 #define MMDC_BASE 0x40ab0000 39 #define IOMUXC1_BASE 0x40ac0000 40 #define MMDC_IO_BASE 0x40ad0000 41 #define PCC3_BASE 0x40b30000 42 #define OCOTP_BASE 0x410A6000 43 #define OCOTP_SIZE 0x4000 44 #define PMC0_BASE 0x410a1000 45 #define SIM_BASE 0x410a3000 46 #define OCOTP_BASE 0x410A6000 47 #define OCOTP_SIZE 0x4000 48 49 #define CAAM_BASE 0x40240000 50 #define CAAM_SIZE 0x10000 51 #define UART4_BASE 0x402d0000 52 #define UART5_BASE 0x402e0000 53 #define UART6_BASE 0x40a60000 54 #define UART7_BASE 0x40a70000 55 56 #define IRAM_BASE 0x1FFFC000 57 #define IRAM_SIZE 0x4000 58 59 #define LP_OCRAM_START IRAM_BASE 60 61 #endif /* __IMX7ULP_H__ */ 62