1 /****************************************************************************** 2 * Filename: hw_aon_wuc_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AON_WUC_H__ 38 #define __HW_AON_WUC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AON_WUC component 44 // 45 //***************************************************************************** 46 // MCU Clock Management 47 #define AON_WUC_O_MCUCLK 0x00000000 48 49 // AUX Clock Management 50 #define AON_WUC_O_AUXCLK 0x00000004 51 52 // MCU Configuration 53 #define AON_WUC_O_MCUCFG 0x00000008 54 55 // AUX Configuration 56 #define AON_WUC_O_AUXCFG 0x0000000C 57 58 // AUX Control 59 #define AON_WUC_O_AUXCTL 0x00000010 60 61 // Power Status 62 #define AON_WUC_O_PWRSTAT 0x00000014 63 64 // Shutdown Control 65 #define AON_WUC_O_SHUTDOWN 0x00000018 66 67 // Control 0 68 #define AON_WUC_O_CTL0 0x00000020 69 70 // Control 1 71 #define AON_WUC_O_CTL1 0x00000024 72 73 // Recharge Controller Configuration 74 #define AON_WUC_O_RECHARGECFG 0x00000030 75 76 // Recharge Controller Status 77 #define AON_WUC_O_RECHARGESTAT 0x00000034 78 79 // Oscillator Configuration 80 #define AON_WUC_O_OSCCFG 0x00000038 81 82 // JTAG Configuration 83 #define AON_WUC_O_JTAGCFG 0x00000040 84 85 // JTAG USERCODE 86 #define AON_WUC_O_JTAGUSERCODE 0x00000044 87 88 //***************************************************************************** 89 // 90 // Register: AON_WUC_O_MCUCLK 91 // 92 //***************************************************************************** 93 // Field: [2] RCOSC_HF_CAL_DONE 94 // 95 // MCU bootcode will set this bit when RCOSC_HF is calibrated. The FLASH can 96 // not be used until this bit is set. 97 // 98 // 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. 99 // 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF 100 // is safe 101 #define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 102 #define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 103 #define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 104 #define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 105 106 // Field: [1:0] PWR_DWN_SRC 107 // 108 // Controls the clock source for the entire MCU domain while MCU is requesting 109 // powerdown. 110 // 111 // When MCU requests powerdown with SCLK_HF as source, then WUC will switch 112 // over to this clock source during powerdown, and automatically switch back to 113 // SCLK_HF when MCU is no longer requesting powerdown and system is back in 114 // active mode. 115 // ENUMs: 116 // SCLK_LF Use SCLK_LF in Powerdown 117 // NONE No clock in Powerdown 118 #define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 119 #define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 120 #define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 121 #define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 122 #define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 123 124 //***************************************************************************** 125 // 126 // Register: AON_WUC_O_AUXCLK 127 // 128 //***************************************************************************** 129 // Field: [12:11] PWR_DWN_SRC 130 // 131 // When AUX requests powerdown with SCLK_HF as source, then WUC will switch 132 // over to this clock source during powerdown, and automatically switch back to 133 // SCLK_HF when AUX system is back in active mode 134 // ENUMs: 135 // SCLK_LF Use SCLK_LF in Powerdown 136 // NONE No clock in Powerdown 137 #define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 138 #define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 139 #define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 140 #define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 141 #define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 142 143 // Field: [10:8] SCLK_HF_DIV 144 // 145 // Select the AUX clock divider for SCLK_HF 146 // 147 // NB: It is not supported to change the AUX clock divider while SCLK_HF is 148 // active source for AUX 149 // ENUMs: 150 // DIV256 Divide by 256 151 // DIV128 Divide by 128 152 // DIV64 Divide by 64 153 // DIV32 Divide by 32 154 // DIV16 Divide by 16 155 // DIV8 Divide by 8 156 // DIV4 Divide by 4 157 // DIV2 Divide by 2 158 #define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 159 #define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 160 #define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 161 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 162 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 163 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 164 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 165 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 166 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 167 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 168 #define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 169 170 // Field: [2:0] SRC 171 // 172 // Selects the clock source for AUX: 173 // 174 // NB: Switching the clock source is guaranteed to be glitchless 175 // ENUMs: 176 // SCLK_LF LF Clock (SCLK_LF) 177 // SCLK_HF HF Clock (SCLK_HF) 178 #define AON_WUC_AUXCLK_SRC_W 3 179 #define AON_WUC_AUXCLK_SRC_M 0x00000007 180 #define AON_WUC_AUXCLK_SRC_S 0 181 #define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 182 #define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 183 184 //***************************************************************************** 185 // 186 // Register: AON_WUC_O_MCUCFG 187 // 188 //***************************************************************************** 189 // Field: [17] VIRT_OFF 190 // 191 // Internal. Only to be used through TI provided API. 192 #define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 193 #define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 194 #define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 195 #define AON_WUC_MCUCFG_VIRT_OFF_S 17 196 197 // Field: [16] FIXED_WU_EN 198 // 199 // Internal. Only to be used through TI provided API. 200 #define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 201 #define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 202 #define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 203 #define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 204 205 // Field: [3:0] SRAM_RET_EN 206 // 207 // MCU SRAM is partitioned into 4 banks . This register controls which of the 208 // banks that has retention during MCU power off 209 // ENUMs: 210 // RET_FULL Retention on for all banks (SRAM:BANK0, SRAM:BANK1 211 // ,SRAM:BANK2 and SRAM:BANK3) 212 // RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 and 213 // SRAM:BANK2 214 // RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 215 // RET_LEVEL1 Retention on for SRAM:BANK0 216 // RET_NONE Retention is disabled 217 #define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 218 #define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F 219 #define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 220 #define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F 221 #define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 222 #define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 223 #define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 224 #define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 225 226 //***************************************************************************** 227 // 228 // Register: AON_WUC_O_AUXCFG 229 // 230 //***************************************************************************** 231 // Field: [0] RAM_RET_EN 232 // 233 // This bit controls retention mode for the AUX_RAM:BANK0: 234 // 235 // 0: Retention is disabled 236 // 1: Retention is enabled 237 // 238 // NB: If retention is disabled, the AUX_RAM will be powered off when it would 239 // otherwise be put in retention mode 240 #define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 241 #define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 242 #define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 243 #define AON_WUC_AUXCFG_RAM_RET_EN_S 0 244 245 //***************************************************************************** 246 // 247 // Register: AON_WUC_O_AUXCTL 248 // 249 //***************************************************************************** 250 // Field: [31] RESET_REQ 251 // 252 // Reset request for AUX. Writing 1 to this register will assert reset to AUX. 253 // The reset will be held until the bit is cleared again. 254 // 255 // 0: AUX reset pin will be deasserted 256 // 1: AUX reset pin will be asserted 257 #define AON_WUC_AUXCTL_RESET_REQ 0x80000000 258 #define AON_WUC_AUXCTL_RESET_REQ_BITN 31 259 #define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 260 #define AON_WUC_AUXCTL_RESET_REQ_S 31 261 262 // Field: [2] SCE_RUN_EN 263 // 264 // Enables (1) or disables (0) AUX_SCE execution. AUX_SCE execution will begin 265 // when AUX Domain is powered and either this or AUX_SCE:CTL.CLK_EN is set. 266 // 267 // Setting this bit will assure that AUX_SCE execution starts as soon as AUX 268 // power domain is woken up. ( AUX_SCE:CTL.CLK_EN will be reset to 0 if AUX 269 // power domain has been off) 270 // 271 // 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 272 // 1: AUX_SCE execution is enabled. 273 #define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 274 #define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 275 #define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 276 #define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 277 278 // Field: [1] SWEV 279 // 280 // Writing 1 sets the software event to the AUX domain, which can be read 281 // through AUX_WUC:WUEVFLAGS.AON_SW. 282 // 283 // This event is normally cleared by AUX_SCE through the 284 // AUX_WUC:WUEVCLR.AON_SW. It can also be cleared by writing 0 to this 285 // register. 286 // 287 // Reading 0 means that there is no outstanding software event for AUX. 288 // 289 // Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from 290 // AUX. 291 #define AON_WUC_AUXCTL_SWEV 0x00000002 292 #define AON_WUC_AUXCTL_SWEV_BITN 1 293 #define AON_WUC_AUXCTL_SWEV_M 0x00000002 294 #define AON_WUC_AUXCTL_SWEV_S 1 295 296 // Field: [0] AUX_FORCE_ON 297 // 298 // Forces the AUX domain into active mode, overriding the requests from 299 // AUX_WUC:PWROFFREQ, AUX_WUC:PWRDWNREQ and AUX_WUC:MCUBUSCTL. 300 // Note that an ongoing AUX_WUC:PWROFFREQ will complete before this bit will 301 // set the AUX domain into active mode. 302 // 303 // MCU must set this bit in order to access the AUX peripherals. 304 // The AUX domain status can be read from PWRSTAT.AUX_PD_ON 305 // 306 // 0: AUX is allowed to Power Off, Power Down or Disconnect. 307 // 1: AUX Power OFF, Power Down or Disconnect requests will be overruled 308 #define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 309 #define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 310 #define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 311 #define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 312 313 //***************************************************************************** 314 // 315 // Register: AON_WUC_O_PWRSTAT 316 // 317 //***************************************************************************** 318 // Field: [9] AUX_PWR_DWN 319 // 320 // Indicates the AUX powerdown state when AUX domain is powered up. 321 // 322 // 0: Active mode 323 // 1: AUX Powerdown request has been granted 324 #define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 325 #define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 326 #define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 327 #define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 328 329 // Field: [6] JTAG_PD_ON 330 // 331 // Indicates JTAG power state: 332 // 333 // 0: JTAG is powered off 334 // 1: JTAG is powered on 335 #define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 336 #define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 337 #define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 338 #define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 339 340 // Field: [5] AUX_PD_ON 341 // 342 // Indicates AUX power state: 343 // 344 // 0: AUX is not ready for use ( may be powered off or in power state 345 // transition ) 346 // 1: AUX is powered on, connected to bus and ready for use, 347 #define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 348 #define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 349 #define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 350 #define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 351 352 // Field: [4] MCU_PD_ON 353 // 354 // Indicates MCU power state: 355 // 356 // 0: MCU Power sequencing is not yet finalized and MCU_AONIF registers may not 357 // be reliable 358 // 1: MCU Power sequencing is finalized and all MCU_AONIF registers are 359 // reliable 360 #define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 361 #define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 362 #define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 363 #define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 364 365 // Field: [2] AUX_BUS_CONNECTED 366 // 367 // Indicates that AUX Bus is connected: 368 // 369 // 0: AUX bus is not connected 370 // 1: AUX bus is connected ( idle_ack = 0 ) 371 #define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 372 #define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 373 #define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 374 #define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 375 376 // Field: [1] AUX_RESET_DONE 377 // 378 // Indicates Reset Done from AUX: 379 // 380 // 0: AUX is being reset 381 // 1: AUX reset is released 382 #define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 383 #define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 384 #define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 385 #define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 386 387 //***************************************************************************** 388 // 389 // Register: AON_WUC_O_SHUTDOWN 390 // 391 //***************************************************************************** 392 // Field: [0] EN 393 // 394 // Writing a 1 to this bit forces a shutdown request to be registered and all 395 // I/O values to be latched - in the PAD ring, possibly enabling I/O wakeup. 396 // Writing 0 will cancel a registered shutdown request and open th I/O latches 397 // residing in the PAD ring. 398 // 399 // A registered shutdown request takes effect the next time power down 400 // conditions exists. At this time, the will not enter Powerdown mode, but 401 // instead it will turn off all internal powersupplies, effectively putting the 402 // device into Shutdown mode. 403 #define AON_WUC_SHUTDOWN_EN 0x00000001 404 #define AON_WUC_SHUTDOWN_EN_BITN 0 405 #define AON_WUC_SHUTDOWN_EN_M 0x00000001 406 #define AON_WUC_SHUTDOWN_EN_S 0 407 408 //***************************************************************************** 409 // 410 // Register: AON_WUC_O_CTL0 411 // 412 //***************************************************************************** 413 // Field: [8] PWR_DWN_DIS 414 // 415 // Controls whether MCU and AUX requesting to be powered off will enable a 416 // transition to powerdown: 417 // 418 // 0: Enabled 419 // 1: Disabled 420 #define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 421 #define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 422 #define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 423 #define AON_WUC_CTL0_PWR_DWN_DIS_S 8 424 425 // Field: [3] AUX_SRAM_ERASE 426 // 427 // Internal. Only to be used through TI provided API. 428 #define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 429 #define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 430 #define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 431 #define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 432 433 // Field: [2] MCU_SRAM_ERASE 434 // 435 // Internal. Only to be used through TI provided API. 436 #define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 437 #define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 438 #define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 439 #define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 440 441 //***************************************************************************** 442 // 443 // Register: AON_WUC_O_CTL1 444 // 445 //***************************************************************************** 446 // Field: [1] MCU_RESET_SRC 447 // 448 // Indicates source of last MCU Voltage Domain warm reset request: 449 // 450 // 0: MCU SW reset 451 // 1: JTAG reset 452 // 453 // This bit can only be cleared by writing a 1 to it 454 #define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 455 #define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 456 #define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 457 #define AON_WUC_CTL1_MCU_RESET_SRC_S 1 458 459 // Field: [0] MCU_WARM_RESET 460 // 461 // Indicates type of last MCU Voltage Domain reset: 462 // 463 // 0: Last MCU reset was not a warm reset 464 // 1: Last MCU reset was a warm reset (requested from MCU or JTAG as indicated 465 // in MCU_RESET_SRC) 466 // 467 // This bit can only be cleared by writing a 1 to it 468 #define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 469 #define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 470 #define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 471 #define AON_WUC_CTL1_MCU_WARM_RESET_S 0 472 473 //***************************************************************************** 474 // 475 // Register: AON_WUC_O_RECHARGECFG 476 // 477 //***************************************************************************** 478 // Field: [31] ADAPTIVE_EN 479 // 480 // Enable adaptive recharge 481 // 482 // Note: Recharge can be turned completely of by setting MAX_PER_E=7 and 483 // MAX_PER_M=31 and this bitfield to 0 484 #define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 485 #define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 486 #define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 487 #define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 488 489 // Field: [23:20] C2 490 // 491 // Gain factor for adaptive recharge algorithm 492 // 493 // period_new=period * ( 1+/-(2^-C1+2^-C2) ) 494 // Valid values for C2 is 2 to 10 495 // 496 // Note: Rounding may cause adaptive recharge not to start for very small 497 // values of both Gain and Initial period. Criteria for algorithm to start is 498 // MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 499 #define AON_WUC_RECHARGECFG_C2_W 4 500 #define AON_WUC_RECHARGECFG_C2_M 0x00F00000 501 #define AON_WUC_RECHARGECFG_C2_S 20 502 503 // Field: [19:16] C1 504 // 505 // Gain factor for adaptive recharge algorithm 506 // 507 // period_new=period * ( 1+/-(2^-C1+2^-C2) ) 508 // Valid values for C1 is 1 to 10 509 // 510 // Note: Rounding may cause adaptive recharge not to start for very small 511 // values of both Gain and Initial period. Criteria for algorithm to start is 512 // MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 513 #define AON_WUC_RECHARGECFG_C1_W 4 514 #define AON_WUC_RECHARGECFG_C1_M 0x000F0000 515 #define AON_WUC_RECHARGECFG_C1_S 16 516 517 // Field: [15:11] MAX_PER_M 518 // 519 // This register defines the maximum period that the recharge algorithm can 520 // take, i.e. it defines the maximum number of cycles between 2 recharges. 521 // The maximum number of cycles is specified with a 5 bit mantissa and 3 bit 522 // exponent: 523 // MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E 524 // This field sets the mantissa of MAXCYCLES 525 #define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 526 #define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 527 #define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 528 529 // Field: [10:8] MAX_PER_E 530 // 531 // This register defines the maximum period that the recharge algorithm can 532 // take, i.e. it defines the maximum number of cycles between 2 recharges. 533 // The maximum number of cycles is specified with a 5 bit mantissa and 3 bit 534 // exponent: 535 // MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E 536 // This field sets the exponent MAXCYCLES 537 #define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 538 #define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 539 #define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 540 541 // Field: [7:3] PER_M 542 // 543 // Number of 32 KHz clocks between activation of recharge controller 544 // For recharge algorithm, PERIOD is the initial period when entering powerdown 545 // mode. The adaptive recharge algorithm will not change this register 546 // PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 547 // bit exponent: 548 // This field sets the Mantissa of the Period. 549 // PERIOD=(PER_M*16+15)*2^PER_E 550 #define AON_WUC_RECHARGECFG_PER_M_W 5 551 #define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 552 #define AON_WUC_RECHARGECFG_PER_M_S 3 553 554 // Field: [2:0] PER_E 555 // 556 // Number of 32 KHz clocks between activation of recharge controller 557 // For recharge algorithm, PERIOD is the initial period when entering powerdown 558 // mode. The adaptive recharge algorithm will not change this register 559 // PERIOD will effectively be a 16 bit value coded in a 5 bit mantissa and 3 560 // bit exponent: 561 // This field sets the Exponent of the Period. 562 // PERIOD=(PER_M*16+15)*2^PER_E 563 #define AON_WUC_RECHARGECFG_PER_E_W 3 564 #define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 565 #define AON_WUC_RECHARGECFG_PER_E_S 0 566 567 //***************************************************************************** 568 // 569 // Register: AON_WUC_O_RECHARGESTAT 570 // 571 //***************************************************************************** 572 // Field: [19:16] VDDR_SMPLS 573 // 574 // The last 4 VDDR samples, bit 0 being the newest. 575 // 576 // The register is being updated in every recharge period with a shift left, 577 // and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case 578 // VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be 579 // shifted in. 580 #define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 581 #define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 582 #define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 583 584 // Field: [15:0] MAX_USED_PER 585 // 586 // The maximum value of recharge period seen with VDDR>threshold. 587 // 588 // The VDDR voltage is compared against the threshold voltage at just before 589 // each recharge. If VDDR is above threshold, MAX_USED_PER is updated with max 590 // ( current recharge peride; MAX_USED_PER ) This way MAX_USED_PER can track 591 // the recharge period where VDDR is decharged to the threshold value. We can 592 // therefore use the value as an indication of the leakage current during 593 // recharge. 594 // 595 // This bitfield is cleared to 0 when writing this register. 596 #define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 597 #define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF 598 #define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 599 600 //***************************************************************************** 601 // 602 // Register: AON_WUC_O_OSCCFG 603 // 604 //***************************************************************************** 605 // Field: [7:3] PER_M 606 // 607 // Number of 32 KHz clocks between oscillator amplitude calibrations. 608 // When this counter expires, an oscillator amplitude compensation is triggered 609 // immediately in Active mode. When this counter expires in Powerdown mode an 610 // internal flag is set such that the amplitude compensation is postponed until 611 // the next recharge occurs. 612 // 613 // The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 614 // 3 bit exponent 615 // PERIOD=(PER_M*16+15)*2^PER_E 616 // This field sets the mantissa 617 // Note: Oscillator amplitude calibration is turned of when both this bitfield 618 // and PER_E are set to 0 619 #define AON_WUC_OSCCFG_PER_M_W 5 620 #define AON_WUC_OSCCFG_PER_M_M 0x000000F8 621 #define AON_WUC_OSCCFG_PER_M_S 3 622 623 // Field: [2:0] PER_E 624 // 625 // Number of 32 KHz clocks between oscillator amplitude calibrations. 626 // When this counter expires, an oscillator amplitude compensation is triggered 627 // immediately in Active mode. When this counter expires in Powerdown mode an 628 // internal flag is set such that the amplitude compensation is postponed until 629 // the next recharge occurs. 630 // The Period will effectively be a 16 bit value coded in a 5 bit mantissa and 631 // 3 bit exponent 632 // PERIOD=(PER_M*16+15)*2^PER_E 633 // This field sets the exponent 634 // Note: Oscillator amplitude calibration is turned of when both PER_M and 635 // this bitfield are set to 0 636 #define AON_WUC_OSCCFG_PER_E_W 3 637 #define AON_WUC_OSCCFG_PER_E_M 0x00000007 638 #define AON_WUC_OSCCFG_PER_E_S 0 639 640 //***************************************************************************** 641 // 642 // Register: AON_WUC_O_JTAGCFG 643 // 644 //***************************************************************************** 645 // Field: [8] JTAG_PD_FORCE_ON 646 // 647 // Controls JTAG PowerDomain power state: 648 // 649 // 0: Controlled exclusively by debug subsystem. (JTAG Powerdomain will be 650 // powered off unless a debugger is attached) 651 // 1: JTAG Power Domain is forced on, independent of debug subsystem. 652 // 653 // NB: The reset value causes JTAG Power Domain to be powered on by default. 654 // Software must clear this bit to turn off the JTAG Power Domain 655 #define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 656 #define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 657 #define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 658 #define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 659 660 //***************************************************************************** 661 // 662 // Register: AON_WUC_O_JTAGUSERCODE 663 // 664 //***************************************************************************** 665 // Field: [31:0] USER_CODE 666 // 667 // 32-bit JTAG USERCODE register feeding main JTAG TAP 668 // NB: This field can be locked 669 #define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 670 #define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF 671 #define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 672 673 674 #endif // __AON_WUC__ 675