1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Adjunct processor (AP) interfaces
4 *
5 * Copyright IBM Corp. 2017
6 *
7 * Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
8 * Martin Schwidefsky <schwidefsky@de.ibm.com>
9 * Harald Freudenberger <freude@de.ibm.com>
10 */
11
12 #ifndef _ASM_S390_AP_H_
13 #define _ASM_S390_AP_H_
14
15 #include <linux/io.h>
16 #include <asm/asm-extable.h>
17
18 /**
19 * The ap_qid_t identifier of an ap queue.
20 * If the AP facilities test (APFT) facility is available,
21 * card and queue index are 8 bit values, otherwise
22 * card index is 6 bit and queue index a 4 bit value.
23 */
24 typedef unsigned int ap_qid_t;
25
26 #define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
27 #define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
28 #define AP_QID_QUEUE(_qid) ((_qid) & 0xff)
29
30 /**
31 * struct ap_queue_status - Holds the AP queue status.
32 * @queue_empty: Shows if queue is empty
33 * @replies_waiting: Waiting replies
34 * @queue_full: Is 1 if the queue is full
35 * @irq_enabled: Shows if interrupts are enabled for the AP
36 * @response_code: Holds the 8 bit response code
37 *
38 * The ap queue status word is returned by all three AP functions
39 * (PQAP, NQAP and DQAP). There's a set of flags in the first
40 * byte, followed by a 1 byte response code.
41 */
42 struct ap_queue_status {
43 unsigned int queue_empty : 1;
44 unsigned int replies_waiting : 1;
45 unsigned int queue_full : 1;
46 unsigned int _pad1 : 4;
47 unsigned int irq_enabled : 1;
48 unsigned int response_code : 8;
49 unsigned int _pad2 : 16;
50 };
51
52 /*
53 * AP queue status reg union to access the reg1
54 * register with the lower 32 bits comprising the
55 * ap queue status.
56 */
57 union ap_queue_status_reg {
58 unsigned long value;
59 struct {
60 u32 _pad;
61 struct ap_queue_status status;
62 };
63 };
64
65 /**
66 * ap_intructions_available() - Test if AP instructions are available.
67 *
68 * Returns true if the AP instructions are installed, otherwise false.
69 */
ap_instructions_available(void)70 static inline bool ap_instructions_available(void)
71 {
72 unsigned long reg0 = AP_MKQID(0, 0);
73 unsigned long reg1 = 0;
74
75 asm volatile(
76 " lgr 0,%[reg0]\n" /* qid into gr0 */
77 " lghi 1,0\n" /* 0 into gr1 */
78 " lghi 2,0\n" /* 0 into gr2 */
79 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
80 "0: la %[reg1],1\n" /* 1 into reg1 */
81 "1:\n"
82 EX_TABLE(0b, 1b)
83 : [reg1] "+&d" (reg1)
84 : [reg0] "d" (reg0)
85 : "cc", "0", "1", "2");
86 return reg1 != 0;
87 }
88
89 /**
90 * ap_tapq(): Test adjunct processor queue.
91 * @qid: The AP queue number
92 * @info: Pointer to queue descriptor
93 *
94 * Returns AP queue status structure.
95 */
ap_tapq(ap_qid_t qid,unsigned long * info)96 static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
97 {
98 union ap_queue_status_reg reg1;
99 unsigned long reg2;
100
101 asm volatile(
102 " lgr 0,%[qid]\n" /* qid into gr0 */
103 " lghi 2,0\n" /* 0 into gr2 */
104 " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
105 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
106 " lgr %[reg2],2\n" /* gr2 into reg2 */
107 : [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2)
108 : [qid] "d" (qid)
109 : "cc", "0", "1", "2");
110 if (info)
111 *info = reg2;
112 return reg1.status;
113 }
114
115 /**
116 * ap_test_queue(): Test adjunct processor queue.
117 * @qid: The AP queue number
118 * @tbit: Test facilities bit
119 * @info: Pointer to queue descriptor
120 *
121 * Returns AP queue status structure.
122 */
ap_test_queue(ap_qid_t qid,int tbit,unsigned long * info)123 static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
124 int tbit,
125 unsigned long *info)
126 {
127 if (tbit)
128 qid |= 1UL << 23; /* set T bit*/
129 return ap_tapq(qid, info);
130 }
131
132 /**
133 * ap_pqap_rapq(): Reset adjunct processor queue.
134 * @qid: The AP queue number
135 *
136 * Returns AP queue status structure.
137 */
ap_rapq(ap_qid_t qid)138 static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
139 {
140 unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */
141 union ap_queue_status_reg reg1;
142
143 asm volatile(
144 " lgr 0,%[reg0]\n" /* qid arg into gr0 */
145 " .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */
146 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
147 : [reg1] "=&d" (reg1.value)
148 : [reg0] "d" (reg0)
149 : "cc", "0", "1");
150 return reg1.status;
151 }
152
153 /**
154 * ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
155 * @qid: The AP queue number
156 *
157 * Returns AP queue status structure.
158 */
ap_zapq(ap_qid_t qid)159 static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
160 {
161 unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */
162 union ap_queue_status_reg reg1;
163
164 asm volatile(
165 " lgr 0,%[reg0]\n" /* qid arg into gr0 */
166 " .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */
167 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
168 : [reg1] "=&d" (reg1.value)
169 : [reg0] "d" (reg0)
170 : "cc", "0", "1");
171 return reg1.status;
172 }
173
174 /**
175 * struct ap_config_info - convenience struct for AP crypto
176 * config info as returned by the ap_qci() function.
177 */
178 struct ap_config_info {
179 unsigned int apsc : 1; /* S bit */
180 unsigned int apxa : 1; /* N bit */
181 unsigned int qact : 1; /* C bit */
182 unsigned int rc8a : 1; /* R bit */
183 unsigned char _reserved1 : 4;
184 unsigned char _reserved2[3];
185 unsigned char Na; /* max # of APs - 1 */
186 unsigned char Nd; /* max # of Domains - 1 */
187 unsigned char _reserved3[10];
188 unsigned int apm[8]; /* AP ID mask */
189 unsigned int aqm[8]; /* AP (usage) queue mask */
190 unsigned int adm[8]; /* AP (control) domain mask */
191 unsigned char _reserved4[16];
192 } __aligned(8);
193
194 /**
195 * ap_qci(): Get AP configuration data
196 *
197 * Returns 0 on success, or -EOPNOTSUPP.
198 */
ap_qci(struct ap_config_info * config)199 static inline int ap_qci(struct ap_config_info *config)
200 {
201 unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */
202 unsigned long reg1 = -EOPNOTSUPP;
203 struct ap_config_info *reg2 = config;
204
205 asm volatile(
206 " lgr 0,%[reg0]\n" /* QCI fc into gr0 */
207 " lgr 2,%[reg2]\n" /* ptr to config into gr2 */
208 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QCI) */
209 "0: la %[reg1],0\n" /* good case, QCI fc available */
210 "1:\n"
211 EX_TABLE(0b, 1b)
212 : [reg1] "+&d" (reg1)
213 : [reg0] "d" (reg0), [reg2] "d" (reg2)
214 : "cc", "memory", "0", "2");
215
216 return reg1;
217 }
218
219 /*
220 * struct ap_qirq_ctrl - convenient struct for easy invocation
221 * of the ap_aqic() function. This struct is passed as GR1
222 * parameter to the PQAP(AQIC) instruction. For details please
223 * see the AR documentation.
224 */
225 union ap_qirq_ctrl {
226 unsigned long value;
227 struct {
228 unsigned int : 8;
229 unsigned int zone : 8; /* zone info */
230 unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
231 unsigned int : 4;
232 unsigned int gisc : 3; /* guest isc field */
233 unsigned int : 6;
234 unsigned int gf : 2; /* gisa format */
235 unsigned int : 1;
236 unsigned int gisa : 27; /* gisa origin */
237 unsigned int : 1;
238 unsigned int isc : 3; /* irq sub class */
239 };
240 };
241
242 /**
243 * ap_aqic(): Control interruption for a specific AP.
244 * @qid: The AP queue number
245 * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
246 * @pa_ind: Physical address of the notification indicator byte
247 *
248 * Returns AP queue status.
249 */
ap_aqic(ap_qid_t qid,union ap_qirq_ctrl qirqctrl,phys_addr_t pa_ind)250 static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
251 union ap_qirq_ctrl qirqctrl,
252 phys_addr_t pa_ind)
253 {
254 unsigned long reg0 = qid | (3UL << 24); /* fc 3UL is AQIC */
255 union ap_queue_status_reg reg1;
256 unsigned long reg2 = pa_ind;
257
258 reg1.value = qirqctrl.value;
259
260 asm volatile(
261 " lgr 0,%[reg0]\n" /* qid param into gr0 */
262 " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
263 " lgr 2,%[reg2]\n" /* ni addr into gr2 */
264 " .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */
265 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
266 : [reg1] "+&d" (reg1.value)
267 : [reg0] "d" (reg0), [reg2] "d" (reg2)
268 : "cc", "memory", "0", "1", "2");
269
270 return reg1.status;
271 }
272
273 /*
274 * union ap_qact_ap_info - used together with the
275 * ap_aqic() function to provide a convenient way
276 * to handle the ap info needed by the qact function.
277 */
278 union ap_qact_ap_info {
279 unsigned long val;
280 struct {
281 unsigned int : 3;
282 unsigned int mode : 3;
283 unsigned int : 26;
284 unsigned int cat : 8;
285 unsigned int : 8;
286 unsigned char ver[2];
287 };
288 };
289
290 /**
291 * ap_qact(): Query AP combatibility type.
292 * @qid: The AP queue number
293 * @apinfo: On input the info about the AP queue. On output the
294 * alternate AP queue info provided by the qact function
295 * in GR2 is stored in.
296 *
297 * Returns AP queue status. Check response_code field for failures.
298 */
ap_qact(ap_qid_t qid,int ifbit,union ap_qact_ap_info * apinfo)299 static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
300 union ap_qact_ap_info *apinfo)
301 {
302 unsigned long reg0 = qid | (5UL << 24) | ((ifbit & 0x01) << 22);
303 union ap_queue_status_reg reg1;
304 unsigned long reg2;
305
306 reg1.value = apinfo->val;
307
308 asm volatile(
309 " lgr 0,%[reg0]\n" /* qid param into gr0 */
310 " lgr 1,%[reg1]\n" /* qact in info into gr1 */
311 " .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */
312 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
313 " lgr %[reg2],2\n" /* qact out info into reg2 */
314 : [reg1] "+&d" (reg1.value), [reg2] "=&d" (reg2)
315 : [reg0] "d" (reg0)
316 : "cc", "0", "1", "2");
317 apinfo->val = reg2;
318 return reg1.status;
319 }
320
321 /**
322 * ap_nqap(): Send message to adjunct processor queue.
323 * @qid: The AP queue number
324 * @psmid: The program supplied message identifier
325 * @msg: The message text
326 * @length: The message length
327 *
328 * Returns AP queue status structure.
329 * Condition code 1 on NQAP can't happen because the L bit is 1.
330 * Condition code 2 on NQAP also means the send is incomplete,
331 * because a segment boundary was reached. The NQAP is repeated.
332 */
ap_nqap(ap_qid_t qid,unsigned long long psmid,void * msg,size_t length)333 static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
334 unsigned long long psmid,
335 void *msg, size_t length)
336 {
337 unsigned long reg0 = qid | 0x40000000UL; /* 0x4... is last msg part */
338 union register_pair nqap_r1, nqap_r2;
339 union ap_queue_status_reg reg1;
340
341 nqap_r1.even = (unsigned int)(psmid >> 32);
342 nqap_r1.odd = psmid & 0xffffffff;
343 nqap_r2.even = (unsigned long)msg;
344 nqap_r2.odd = (unsigned long)length;
345
346 asm volatile (
347 " lgr 0,%[reg0]\n" /* qid param in gr0 */
348 "0: .insn rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n"
349 " brc 2,0b\n" /* handle partial completion */
350 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
351 : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),
352 [nqap_r2] "+&d" (nqap_r2.pair)
353 : [nqap_r1] "d" (nqap_r1.pair)
354 : "cc", "memory", "0", "1");
355 return reg1.status;
356 }
357
358 /**
359 * ap_dqap(): Receive message from adjunct processor queue.
360 * @qid: The AP queue number
361 * @psmid: Pointer to program supplied message identifier
362 * @msg: The message text
363 * @length: The message length
364 * @reslength: Resitual length on return
365 * @resgr0: input: gr0 value (only used if != 0), output: resitual gr0 content
366 *
367 * Returns AP queue status structure.
368 * Condition code 1 on DQAP means the receive has taken place
369 * but only partially. The response is incomplete, hence the
370 * DQAP is repeated.
371 * Condition code 2 on DQAP also means the receive is incomplete,
372 * this time because a segment boundary was reached. Again, the
373 * DQAP is repeated.
374 * Note that gpr2 is used by the DQAP instruction to keep track of
375 * any 'residual' length, in case the instruction gets interrupted.
376 * Hence it gets zeroed before the instruction.
377 * If the message does not fit into the buffer, this function will
378 * return with a truncated message and the reply in the firmware queue
379 * is not removed. This is indicated to the caller with an
380 * ap_queue_status response_code value of all bits on (0xFF) and (if
381 * the reslength ptr is given) the remaining length is stored in
382 * *reslength and (if the resgr0 ptr is given) the updated gr0 value
383 * for further processing of this msg entry is stored in *resgr0. The
384 * caller needs to detect this situation and should invoke ap_dqap
385 * with a valid resgr0 ptr and a value in there != 0 to indicate that
386 * *resgr0 is to be used instead of qid to further process this entry.
387 */
ap_dqap(ap_qid_t qid,unsigned long long * psmid,void * msg,size_t length,size_t * reslength,unsigned long * resgr0)388 static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
389 unsigned long long *psmid,
390 void *msg, size_t length,
391 size_t *reslength,
392 unsigned long *resgr0)
393 {
394 unsigned long reg0 = resgr0 && *resgr0 ? *resgr0 : qid | 0x80000000UL;
395 union ap_queue_status_reg reg1;
396 unsigned long reg2;
397 union register_pair rp1, rp2;
398
399 rp1.even = 0UL;
400 rp1.odd = 0UL;
401 rp2.even = (unsigned long)msg;
402 rp2.odd = (unsigned long)length;
403
404 asm volatile(
405 " lgr 0,%[reg0]\n" /* qid param into gr0 */
406 " lghi 2,0\n" /* 0 into gr2 (res length) */
407 "0: ltgr %N[rp2],%N[rp2]\n" /* check buf len */
408 " jz 2f\n" /* go out if buf len is 0 */
409 "1: .insn rre,0xb2ae0000,%[rp1],%[rp2]\n"
410 " brc 6,0b\n" /* handle partial complete */
411 "2: lgr %[reg0],0\n" /* gr0 (qid + info) into reg0 */
412 " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
413 " lgr %[reg2],2\n" /* gr2 (res length) into reg2 */
414 : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),
415 [reg2] "=&d" (reg2), [rp1] "+&d" (rp1.pair),
416 [rp2] "+&d" (rp2.pair)
417 :
418 : "cc", "memory", "0", "1", "2");
419
420 if (reslength)
421 *reslength = reg2;
422 if (reg2 != 0 && rp2.odd == 0) {
423 /*
424 * Partially complete, status in gr1 is not set.
425 * Signal the caller that this dqap is only partially received
426 * with a special status response code 0xFF and *resgr0 updated
427 */
428 reg1.status.response_code = 0xFF;
429 if (resgr0)
430 *resgr0 = reg0;
431 } else {
432 *psmid = (((unsigned long long)rp1.even) << 32) + rp1.odd;
433 if (resgr0)
434 *resgr0 = 0;
435 }
436
437 return reg1.status;
438 }
439
440 /*
441 * Interface to tell the AP bus code that a configuration
442 * change has happened. The bus code should at least do
443 * an ap bus resource rescan.
444 */
445 #if IS_ENABLED(CONFIG_ZCRYPT)
446 void ap_bus_cfg_chg(void);
447 #else
ap_bus_cfg_chg(void)448 static inline void ap_bus_cfg_chg(void){}
449 #endif
450
451 #endif /* _ASM_S390_AP_H_ */
452