1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key hash lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 28 /* Special value used to verify platform parameters from BL2 to BL31 */ 29 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 30 31 #define ARM_SYSTEM_COUNT U(1) 32 33 #define ARM_CACHE_WRITEBACK_SHIFT 6 34 35 /* 36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 37 * power levels have a 1:1 mapping with the MPIDR affinity levels. 38 */ 39 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 40 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 41 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 42 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 43 44 /* 45 * Macros for local power states in ARM platforms encoded by State-ID field 46 * within the power-state parameter. 47 */ 48 /* Local power state for power domains in Run state. */ 49 #define ARM_LOCAL_STATE_RUN U(0) 50 /* Local power state for retention. Valid only for CPU power domains */ 51 #define ARM_LOCAL_STATE_RET U(1) 52 /* Local power state for OFF/power-down. Valid for CPU and cluster power 53 domains */ 54 #define ARM_LOCAL_STATE_OFF U(2) 55 56 /* Memory location options for TSP */ 57 #define ARM_TRUSTED_SRAM_ID 0 58 #define ARM_TRUSTED_DRAM_ID 1 59 #define ARM_DRAM_ID 2 60 61 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 62 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 63 #else 64 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 65 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 66 67 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 68 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 69 70 /* The remaining Trusted SRAM is used to load the BL images */ 71 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 72 ARM_SHARED_RAM_SIZE) 73 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 74 ARM_SHARED_RAM_SIZE) 75 76 /* 77 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 78 * follows: 79 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 80 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 81 * - REALM DRAM: Reserved for Realm world if RME is enabled 82 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 83 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 84 * 85 * RME enabled(64MB) RME not enabled(16MB) 86 * -------------------- ------------------- 87 * | | | | 88 * | AP TZC (~28MB) | | AP TZC (~14MB) | 89 * -------------------- ------------------- 90 * | | | | 91 * | REALM (RMM) | | EL3 TZC (2MB) | 92 * | (32MB - 4KB) | ------------------- 93 * -------------------- | | 94 * | | | SCP TZC | 95 * | TF-A <-> RMM | 0xFFFF_FFFF------------------- 96 * | SHARED (4KB) | 97 * -------------------- 98 * | | 99 * | EL3 TZC (3MB) | 100 * -------------------- 101 * | L1 GPT + SCP TZC | 102 * | (~1MB) | 103 * 0xFFFF_FFFF -------------------- 104 */ 105 #if ENABLE_RME 106 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 107 /* 108 * Define a region within the TZC secured DRAM for use by EL3 runtime 109 * firmware. This region is meant to be NOLOAD and will not be zero 110 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 111 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 112 */ 113 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 114 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 115 116 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 117 #define ARM_REALM_SIZE (UL(0x02000000) - \ 118 ARM_EL3_RMM_SHARED_SIZE) 119 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 120 #else 121 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 122 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 123 #define ARM_L1_GPT_SIZE UL(0) 124 #define ARM_REALM_SIZE UL(0) 125 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 126 #endif /* ENABLE_RME */ 127 128 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 129 ARM_DRAM1_SIZE - \ 130 (ARM_SCP_TZC_DRAM1_SIZE + \ 131 ARM_L1_GPT_SIZE)) 132 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 133 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 134 ARM_SCP_TZC_DRAM1_SIZE - 1U) 135 #if ENABLE_RME 136 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 137 ARM_DRAM1_SIZE - \ 138 ARM_L1_GPT_SIZE) 139 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 140 ARM_L1_GPT_SIZE - 1U) 141 142 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 143 ARM_REALM_SIZE) 144 145 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 146 147 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 148 ARM_DRAM1_SIZE - \ 149 (ARM_SCP_TZC_DRAM1_SIZE + \ 150 ARM_L1_GPT_SIZE + \ 151 ARM_EL3_RMM_SHARED_SIZE + \ 152 ARM_EL3_TZC_DRAM1_SIZE)) 153 154 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 155 ARM_EL3_RMM_SHARED_SIZE - 1U) 156 #endif /* ENABLE_RME */ 157 158 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 159 ARM_EL3_TZC_DRAM1_SIZE) 160 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 161 ARM_EL3_TZC_DRAM1_SIZE - 1U) 162 163 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 164 ARM_DRAM1_SIZE - \ 165 ARM_TZC_DRAM1_SIZE) 166 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 167 (ARM_SCP_TZC_DRAM1_SIZE + \ 168 ARM_EL3_TZC_DRAM1_SIZE + \ 169 ARM_EL3_RMM_SHARED_SIZE + \ 170 ARM_REALM_SIZE + \ 171 ARM_L1_GPT_SIZE)) 172 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 173 ARM_AP_TZC_DRAM1_SIZE - 1U) 174 175 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 176 #if ARM_CRYPTOCELL_INTEG 177 /* 178 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 179 * This is required by CryptoCell to authenticate BL33 which is loaded 180 * into the Non Secure DDR. 181 */ 182 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 183 #else 184 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 185 #endif 186 187 #ifdef SPD_opteed 188 /* 189 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 190 * load/authenticate the trusted os extra image. The first 512KB of 191 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 192 * for OPTEE is paged image which only include the paging part using 193 * virtual memory but without "init" data. OPTEE will copy the "init" data 194 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 195 * extra image behind the "init" data. 196 */ 197 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 198 ARM_AP_TZC_DRAM1_SIZE - \ 199 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 200 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 201 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 202 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 203 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 204 MT_MEMORY | MT_RW | MT_SECURE) 205 206 /* 207 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 208 * support is enabled). 209 */ 210 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 211 BL32_BASE, \ 212 BL32_LIMIT - BL32_BASE, \ 213 MT_MEMORY | MT_RW | MT_SECURE) 214 #endif /* SPD_opteed */ 215 216 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 217 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 218 ARM_TZC_DRAM1_SIZE) 219 220 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 221 ARM_NS_DRAM1_SIZE - 1U) 222 #ifdef PLAT_ARM_DRAM1_BASE 223 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 224 #else 225 #define ARM_DRAM1_BASE ULL(0x80000000) 226 #endif /* PLAT_ARM_DRAM1_BASE */ 227 228 #define ARM_DRAM1_SIZE ULL(0x80000000) 229 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 230 ARM_DRAM1_SIZE - 1U) 231 232 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 233 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 234 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 235 ARM_DRAM2_SIZE - 1U) 236 237 #define ARM_IRQ_SEC_PHY_TIMER 29 238 239 #define ARM_IRQ_SEC_SGI_0 8 240 #define ARM_IRQ_SEC_SGI_1 9 241 #define ARM_IRQ_SEC_SGI_2 10 242 #define ARM_IRQ_SEC_SGI_3 11 243 #define ARM_IRQ_SEC_SGI_4 12 244 #define ARM_IRQ_SEC_SGI_5 13 245 #define ARM_IRQ_SEC_SGI_6 14 246 #define ARM_IRQ_SEC_SGI_7 15 247 248 /* 249 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 250 * terminology. On a GICv2 system or mode, the lists will be merged and treated 251 * as Group 0 interrupts. 252 */ 253 #define ARM_G1S_IRQ_PROPS(grp) \ 254 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 255 GIC_INTR_CFG_LEVEL), \ 256 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 257 GIC_INTR_CFG_EDGE), \ 258 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 259 GIC_INTR_CFG_EDGE), \ 260 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 261 GIC_INTR_CFG_EDGE), \ 262 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 263 GIC_INTR_CFG_EDGE), \ 264 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 265 GIC_INTR_CFG_EDGE), \ 266 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 267 GIC_INTR_CFG_EDGE) 268 269 #define ARM_G0_IRQ_PROPS(grp) \ 270 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 271 GIC_INTR_CFG_EDGE), \ 272 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 273 GIC_INTR_CFG_EDGE) 274 275 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 276 ARM_SHARED_RAM_BASE, \ 277 ARM_SHARED_RAM_SIZE, \ 278 MT_DEVICE | MT_RW | EL3_PAS) 279 280 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 281 ARM_NS_DRAM1_BASE, \ 282 ARM_NS_DRAM1_SIZE, \ 283 MT_MEMORY | MT_RW | MT_NS) 284 285 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 286 ARM_DRAM2_BASE, \ 287 ARM_DRAM2_SIZE, \ 288 MT_MEMORY | MT_RW | MT_NS) 289 290 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 291 TSP_SEC_MEM_BASE, \ 292 TSP_SEC_MEM_SIZE, \ 293 MT_MEMORY | MT_RW | MT_SECURE) 294 295 #if ARM_BL31_IN_DRAM 296 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 297 BL31_BASE, \ 298 PLAT_ARM_MAX_BL31_SIZE, \ 299 MT_MEMORY | MT_RW | MT_SECURE) 300 #endif 301 302 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 303 ARM_EL3_TZC_DRAM1_BASE, \ 304 ARM_EL3_TZC_DRAM1_SIZE, \ 305 MT_MEMORY | MT_RW | EL3_PAS) 306 307 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 308 PLAT_ARM_TRUSTED_DRAM_BASE, \ 309 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 310 MT_MEMORY | MT_RW | MT_SECURE) 311 312 #if ENABLE_RME 313 /* 314 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 315 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 316 */ 317 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 318 PLAT_ARM_RMM_BASE, \ 319 (PLAT_ARM_RMM_SIZE + \ 320 ARM_EL3_RMM_SHARED_SIZE), \ 321 MT_MEMORY | MT_RW | MT_REALM) 322 323 324 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 325 ARM_L1_GPT_ADDR_BASE, \ 326 ARM_L1_GPT_SIZE, \ 327 MT_MEMORY | MT_RW | EL3_PAS) 328 329 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 330 MAP_REGION_FLAT( \ 331 ARM_EL3_RMM_SHARED_BASE, \ 332 ARM_EL3_RMM_SHARED_SIZE, \ 333 MT_MEMORY | MT_RW | MT_REALM) 334 335 #endif /* ENABLE_RME */ 336 337 /* 338 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 339 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 340 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 341 * to be able to access the heap. 342 */ 343 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 344 BL1_RW_BASE, \ 345 BL1_RW_LIMIT - BL1_RW_BASE, \ 346 MT_MEMORY | MT_RW | EL3_PAS) 347 348 /* 349 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 350 * otherwise one region is defined containing both. 351 */ 352 #if SEPARATE_CODE_AND_RODATA 353 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 354 BL_CODE_BASE, \ 355 BL_CODE_END - BL_CODE_BASE, \ 356 MT_CODE | EL3_PAS), \ 357 MAP_REGION_FLAT( \ 358 BL_RO_DATA_BASE, \ 359 BL_RO_DATA_END \ 360 - BL_RO_DATA_BASE, \ 361 MT_RO_DATA | EL3_PAS) 362 #else 363 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 364 BL_CODE_BASE, \ 365 BL_CODE_END - BL_CODE_BASE, \ 366 MT_CODE | EL3_PAS) 367 #endif 368 #if USE_COHERENT_MEM 369 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 370 BL_COHERENT_RAM_BASE, \ 371 BL_COHERENT_RAM_END \ 372 - BL_COHERENT_RAM_BASE, \ 373 MT_DEVICE | MT_RW | EL3_PAS) 374 #endif 375 #if USE_ROMLIB 376 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 377 ROMLIB_RO_BASE, \ 378 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 379 MT_CODE | EL3_PAS) 380 381 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 382 ROMLIB_RW_BASE, \ 383 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 384 MT_MEMORY | MT_RW | EL3_PAS) 385 #endif 386 387 /* 388 * Map mem_protect flash region with read and write permissions 389 */ 390 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 391 V2M_FLASH_BLOCK_SIZE, \ 392 MT_DEVICE | MT_RW | MT_SECURE) 393 /* 394 * Map the region for device tree configuration with read and write permissions 395 */ 396 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 397 (ARM_FW_CONFIGS_LIMIT \ 398 - ARM_BL_RAM_BASE), \ 399 MT_MEMORY | MT_RW | EL3_PAS) 400 /* 401 * Map L0_GPT with read and write permissions 402 */ 403 #if ENABLE_RME 404 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 405 ARM_L0_GPT_SIZE, \ 406 MT_MEMORY | MT_RW | MT_ROOT) 407 #endif 408 409 /* 410 * The max number of regions like RO(code), coherent and data required by 411 * different BL stages which need to be mapped in the MMU. 412 */ 413 #define ARM_BL_REGIONS 7 414 415 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 416 ARM_BL_REGIONS) 417 418 /* Memory mapped Generic timer interfaces */ 419 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 420 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 421 #else 422 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 423 #endif 424 425 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 426 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 427 #else 428 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 429 #endif 430 431 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 432 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 433 #else 434 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 435 #endif 436 437 #ifdef PLAT_ARM_SYS_CNT_BASE_S 438 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 439 #else 440 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 441 #endif 442 443 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 444 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 445 #else 446 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 447 #endif 448 449 #define ARM_CONSOLE_BAUDRATE 115200 450 451 /* Trusted Watchdog constants */ 452 #ifdef PLAT_ARM_SP805_TWDG_BASE 453 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 454 #else 455 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 456 #endif 457 #define ARM_SP805_TWDG_CLK_HZ 32768 458 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 459 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 460 #define ARM_TWDG_TIMEOUT_SEC 128 461 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 462 ARM_TWDG_TIMEOUT_SEC) 463 464 /****************************************************************************** 465 * Required platform porting definitions common to all ARM standard platforms 466 *****************************************************************************/ 467 468 /* 469 * This macro defines the deepest retention state possible. A higher state 470 * id will represent an invalid or a power down state. 471 */ 472 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 473 474 /* 475 * This macro defines the deepest power down states possible. Any state ID 476 * higher than this is invalid. 477 */ 478 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 479 480 /* 481 * Some data must be aligned on the biggest cache line size in the platform. 482 * This is known only to the platform as it might have a combination of 483 * integrated and external caches. 484 */ 485 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 486 487 /* 488 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 489 * and limit. Leave enough space of BL2 meminfo. 490 */ 491 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 492 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 493 + (PAGE_SIZE / 2U)) 494 495 /* 496 * Boot parameters passed from BL2 to BL31/BL32 are stored here 497 */ 498 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 499 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 500 + (PAGE_SIZE / 2U)) 501 502 /* 503 * Define limit of firmware configuration memory: 504 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 505 */ 506 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 507 508 #if ENABLE_RME 509 /* 510 * Store the L0 GPT on Trusted SRAM next to firmware 511 * configuration memory, 4KB aligned. 512 */ 513 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 514 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 515 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 516 #else 517 #define ARM_L0_GPT_SIZE U(0) 518 #endif 519 520 /******************************************************************************* 521 * BL1 specific defines. 522 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 523 * addresses. 524 ******************************************************************************/ 525 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 526 #ifdef PLAT_BL1_RO_LIMIT 527 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 528 #else 529 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 530 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 531 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 532 #endif 533 534 /* 535 * Put BL1 RW at the top of the Trusted SRAM. 536 */ 537 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 538 ARM_BL_RAM_SIZE - \ 539 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 540 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 541 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 542 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 543 544 #define ROMLIB_RO_BASE BL1_RO_LIMIT 545 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 546 547 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 548 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 549 550 /******************************************************************************* 551 * BL2 specific defines. 552 ******************************************************************************/ 553 #if BL2_AT_EL3 554 #if ENABLE_PIE 555 /* 556 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 557 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 558 */ 559 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 560 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 561 0x3000) 562 #else 563 /* Put BL2 towards the middle of the Trusted SRAM */ 564 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 565 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 566 0x2000) 567 #endif /* ENABLE_PIE */ 568 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 569 570 #else 571 /* 572 * Put BL2 just below BL1. 573 */ 574 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 575 #define BL2_LIMIT BL1_RW_BASE 576 #endif 577 578 /******************************************************************************* 579 * BL31 specific defines. 580 ******************************************************************************/ 581 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 582 /* 583 * Put BL31 at the bottom of TZC secured DRAM 584 */ 585 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 586 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 587 PLAT_ARM_MAX_BL31_SIZE) 588 /* 589 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 590 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 591 */ 592 #if SEPARATE_NOBITS_REGION 593 #define BL31_NOBITS_BASE BL2_BASE 594 #define BL31_NOBITS_LIMIT BL2_LIMIT 595 #endif /* SEPARATE_NOBITS_REGION */ 596 #elif (RESET_TO_BL31) 597 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 598 # if !ENABLE_PIE 599 # error "BL31 must be a PIE if RESET_TO_BL31=1." 600 #endif 601 /* 602 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 603 * used for building BL31 and not used for loading BL31. 604 */ 605 # define BL31_BASE 0x0 606 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 607 #else 608 /* Put BL31 below BL2 in the Trusted SRAM.*/ 609 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 610 - PLAT_ARM_MAX_BL31_SIZE) 611 #define BL31_PROGBITS_LIMIT BL2_BASE 612 /* 613 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 614 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 615 */ 616 #if BL2_AT_EL3 617 #define BL31_LIMIT BL2_BASE 618 #else 619 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 620 #endif 621 #endif 622 623 /****************************************************************************** 624 * RMM specific defines 625 *****************************************************************************/ 626 #if ENABLE_RME 627 #define RMM_BASE (ARM_REALM_BASE) 628 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 629 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 630 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 631 #endif 632 633 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 634 /******************************************************************************* 635 * BL32 specific defines for EL3 runtime in AArch32 mode 636 ******************************************************************************/ 637 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 638 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 639 # if !ENABLE_PIE 640 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 641 #endif 642 /* 643 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 644 * used for building BL32 and not used for loading BL32. 645 */ 646 # define BL32_BASE 0x0 647 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 648 # else 649 /* Put BL32 below BL2 in the Trusted SRAM.*/ 650 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 651 - PLAT_ARM_MAX_BL32_SIZE) 652 # define BL32_PROGBITS_LIMIT BL2_BASE 653 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 654 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 655 656 #else 657 /******************************************************************************* 658 * BL32 specific defines for EL3 runtime in AArch64 mode 659 ******************************************************************************/ 660 /* 661 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 662 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 663 * controller. 664 */ 665 # if SPM_MM || SPMC_AT_EL3 666 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 667 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 668 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 669 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 670 ARM_AP_TZC_DRAM1_SIZE) 671 # elif defined(SPD_spmd) 672 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 673 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 674 # define BL32_BASE PLAT_ARM_SPMC_BASE 675 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 676 PLAT_ARM_SPMC_SIZE) 677 # elif ARM_BL31_IN_DRAM 678 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 679 PLAT_ARM_MAX_BL31_SIZE) 680 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 681 PLAT_ARM_MAX_BL31_SIZE) 682 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 683 PLAT_ARM_MAX_BL31_SIZE) 684 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 685 ARM_AP_TZC_DRAM1_SIZE) 686 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 687 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 688 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 689 # define TSP_PROGBITS_LIMIT BL31_BASE 690 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 691 # define BL32_LIMIT BL31_BASE 692 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 693 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 694 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 695 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 696 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 697 + (UL(1) << 21)) 698 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 699 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 700 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 701 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 702 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 703 ARM_AP_TZC_DRAM1_SIZE) 704 # else 705 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 706 # endif 707 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 708 709 /* 710 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 711 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 712 * used as BL32. 713 */ 714 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 715 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 716 # undef BL32_BASE 717 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 718 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 719 720 /******************************************************************************* 721 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 722 ******************************************************************************/ 723 #define BL2U_BASE BL2_BASE 724 #define BL2U_LIMIT BL2_LIMIT 725 726 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 727 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 728 729 /* 730 * ID of the secure physical generic timer interrupt used by the TSP. 731 */ 732 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 733 734 735 /* 736 * One cache line needed for bakery locks on ARM platforms 737 */ 738 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 739 740 /* Priority levels for ARM platforms */ 741 #define PLAT_RAS_PRI 0x10 742 #define PLAT_SDEI_CRITICAL_PRI 0x60 743 #define PLAT_SDEI_NORMAL_PRI 0x70 744 745 /* ARM platforms use 3 upper bits of secure interrupt priority */ 746 #define PLAT_PRI_BITS 3 747 748 /* SGI used for SDEI signalling */ 749 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 750 751 #if SDEI_IN_FCONF 752 /* ARM SDEI dynamic private event max count */ 753 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 754 755 /* ARM SDEI dynamic shared event max count */ 756 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 757 #else 758 /* ARM SDEI dynamic private event numbers */ 759 #define ARM_SDEI_DP_EVENT_0 1000 760 #define ARM_SDEI_DP_EVENT_1 1001 761 #define ARM_SDEI_DP_EVENT_2 1002 762 763 /* ARM SDEI dynamic shared event numbers */ 764 #define ARM_SDEI_DS_EVENT_0 2000 765 #define ARM_SDEI_DS_EVENT_1 2001 766 #define ARM_SDEI_DS_EVENT_2 2002 767 768 #define ARM_SDEI_PRIVATE_EVENTS \ 769 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 770 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 771 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 772 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 773 774 #define ARM_SDEI_SHARED_EVENTS \ 775 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 776 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 777 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 778 #endif /* SDEI_IN_FCONF */ 779 780 #endif /* ARM_DEF_H */ 781