1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * The above copyright notice and this permission notice (including the
21  * next paragraph) shall be included in all copies or substantial portions
22  * of the Software.
23  *
24  */
25 /*
26  * Authors: Dave Airlie <airlied@redhat.com>
27  */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30 
31 #include <linux/i2c.h>
32 #include <linux/i2c-algo-bit.h>
33 #include <linux/io.h>
34 #include <linux/types.h>
35 
36 #include <drm/drm_connector.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_mode.h>
40 #include <drm/drm_framebuffer.h>
41 
42 #define DRIVER_AUTHOR		"Dave Airlie"
43 
44 #define DRIVER_NAME		"ast"
45 #define DRIVER_DESC		"AST"
46 #define DRIVER_DATE		"20120228"
47 
48 #define DRIVER_MAJOR		0
49 #define DRIVER_MINOR		1
50 #define DRIVER_PATCHLEVEL	0
51 
52 #define PCI_CHIP_AST2000 0x2000
53 #define PCI_CHIP_AST2100 0x2010
54 
55 
56 enum ast_chip {
57 	AST2000,
58 	AST2100,
59 	AST1100,
60 	AST2200,
61 	AST2150,
62 	AST2300,
63 	AST2400,
64 	AST2500,
65 	AST2600,
66 };
67 
68 enum ast_tx_chip {
69 	AST_TX_NONE,
70 	AST_TX_SIL164,
71 	AST_TX_DP501,
72 	AST_TX_ASTDP,
73 };
74 
75 #define AST_TX_NONE_BIT		BIT(AST_TX_NONE)
76 #define AST_TX_SIL164_BIT	BIT(AST_TX_SIL164)
77 #define AST_TX_DP501_BIT	BIT(AST_TX_DP501)
78 #define AST_TX_ASTDP_BIT	BIT(AST_TX_ASTDP)
79 
80 #define AST_DRAM_512Mx16 0
81 #define AST_DRAM_1Gx16   1
82 #define AST_DRAM_512Mx32 2
83 #define AST_DRAM_1Gx32   3
84 #define AST_DRAM_2Gx16   6
85 #define AST_DRAM_4Gx16   7
86 #define AST_DRAM_8Gx16   8
87 
88 /*
89  * Hardware cursor
90  */
91 
92 #define AST_MAX_HWC_WIDTH	64
93 #define AST_MAX_HWC_HEIGHT	64
94 
95 #define AST_HWC_SIZE		(AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
96 #define AST_HWC_SIGNATURE_SIZE	32
97 
98 /* define for signature structure */
99 #define AST_HWC_SIGNATURE_CHECKSUM	0x00
100 #define AST_HWC_SIGNATURE_SizeX		0x04
101 #define AST_HWC_SIGNATURE_SizeY		0x08
102 #define AST_HWC_SIGNATURE_X		0x0C
103 #define AST_HWC_SIGNATURE_Y		0x10
104 #define AST_HWC_SIGNATURE_HOTSPOTX	0x14
105 #define AST_HWC_SIGNATURE_HOTSPOTY	0x18
106 
107 /*
108  * Planes
109  */
110 
111 struct ast_plane {
112 	struct drm_plane base;
113 
114 	void __iomem *vaddr;
115 	u64 offset;
116 	unsigned long size;
117 };
118 
to_ast_plane(struct drm_plane * plane)119 static inline struct ast_plane *to_ast_plane(struct drm_plane *plane)
120 {
121 	return container_of(plane, struct ast_plane, base);
122 }
123 
124 /*
125  * Connector with i2c channel
126  */
127 
128 struct ast_i2c_chan {
129 	struct i2c_adapter adapter;
130 	struct drm_device *dev;
131 	struct i2c_algo_bit_data bit;
132 };
133 
134 struct ast_vga_connector {
135 	struct drm_connector base;
136 	struct ast_i2c_chan *i2c;
137 };
138 
139 static inline struct ast_vga_connector *
to_ast_vga_connector(struct drm_connector * connector)140 to_ast_vga_connector(struct drm_connector *connector)
141 {
142 	return container_of(connector, struct ast_vga_connector, base);
143 }
144 
145 struct ast_sil164_connector {
146 	struct drm_connector base;
147 	struct ast_i2c_chan *i2c;
148 };
149 
150 static inline struct ast_sil164_connector *
to_ast_sil164_connector(struct drm_connector * connector)151 to_ast_sil164_connector(struct drm_connector *connector)
152 {
153 	return container_of(connector, struct ast_sil164_connector, base);
154 }
155 
156 /*
157  * Device
158  */
159 
160 struct ast_private {
161 	struct drm_device base;
162 
163 	struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */
164 	void __iomem *regs;
165 	void __iomem *ioregs;
166 	void __iomem *dp501_fw_buf;
167 
168 	enum ast_chip chip;
169 	bool vga2_clone;
170 	uint32_t dram_bus_width;
171 	uint32_t dram_type;
172 	uint32_t mclk;
173 
174 	void __iomem	*vram;
175 	unsigned long	vram_base;
176 	unsigned long	vram_size;
177 	unsigned long	vram_fb_available;
178 
179 	struct ast_plane primary_plane;
180 	struct ast_plane cursor_plane;
181 	struct drm_crtc crtc;
182 	struct {
183 		struct {
184 			struct drm_encoder encoder;
185 			struct ast_vga_connector vga_connector;
186 		} vga;
187 		struct {
188 			struct drm_encoder encoder;
189 			struct ast_sil164_connector sil164_connector;
190 		} sil164;
191 		struct {
192 			struct drm_encoder encoder;
193 			struct drm_connector connector;
194 		} dp501;
195 		struct {
196 			struct drm_encoder encoder;
197 			struct drm_connector connector;
198 		} astdp;
199 	} output;
200 
201 	bool support_wide_screen;
202 	enum {
203 		ast_use_p2a,
204 		ast_use_dt,
205 		ast_use_defaults
206 	} config_mode;
207 
208 	unsigned long tx_chip_types;		/* bitfield of enum ast_chip_type */
209 	u8 *dp501_fw_addr;
210 	const struct firmware *dp501_fw;	/* dp501 fw */
211 };
212 
to_ast_private(struct drm_device * dev)213 static inline struct ast_private *to_ast_private(struct drm_device *dev)
214 {
215 	return container_of(dev, struct ast_private, base);
216 }
217 
218 struct ast_private *ast_device_create(const struct drm_driver *drv,
219 				      struct pci_dev *pdev,
220 				      unsigned long flags);
221 
222 #define AST_IO_AR_PORT_WRITE		(0x40)
223 #define AST_IO_MISC_PORT_WRITE		(0x42)
224 #define AST_IO_VGA_ENABLE_PORT		(0x43)
225 #define AST_IO_SEQ_PORT			(0x44)
226 #define AST_IO_DAC_INDEX_READ		(0x47)
227 #define AST_IO_DAC_INDEX_WRITE		(0x48)
228 #define AST_IO_DAC_DATA		        (0x49)
229 #define AST_IO_GR_PORT			(0x4E)
230 #define AST_IO_CRTC_PORT		(0x54)
231 #define AST_IO_INPUT_STATUS1_READ	(0x5A)
232 #define AST_IO_MISC_PORT_READ		(0x4C)
233 
234 #define AST_IO_MM_OFFSET		(0x380)
235 
236 #define AST_IO_VGAIR1_VREFRESH		BIT(3)
237 
238 #define AST_IO_VGACRCB_HWC_ENABLED     BIT(1)
239 #define AST_IO_VGACRCB_HWC_16BPP       BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
240 
241 #define __ast_read(x) \
242 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
243 u##x val = 0;\
244 val = ioread##x(ast->regs + reg); \
245 return val;\
246 }
247 
248 __ast_read(8);
249 __ast_read(16);
250 __ast_read(32)
251 
252 #define __ast_io_read(x) \
253 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
254 u##x val = 0;\
255 val = ioread##x(ast->ioregs + reg); \
256 return val;\
257 }
258 
259 __ast_io_read(8);
260 __ast_io_read(16);
261 __ast_io_read(32);
262 
263 #define __ast_write(x) \
264 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
265 	iowrite##x(val, ast->regs + reg);\
266 	}
267 
268 __ast_write(8);
269 __ast_write(16);
270 __ast_write(32);
271 
272 #define __ast_io_write(x) \
273 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
274 	iowrite##x(val, ast->ioregs + reg);\
275 	}
276 
277 __ast_io_write(8);
278 __ast_io_write(16);
279 #undef __ast_io_write
280 
ast_set_index_reg(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t val)281 static inline void ast_set_index_reg(struct ast_private *ast,
282 				     uint32_t base, uint8_t index,
283 				     uint8_t val)
284 {
285 	ast_io_write16(ast, base, ((u16)val << 8) | index);
286 }
287 
288 void ast_set_index_reg_mask(struct ast_private *ast,
289 			    uint32_t base, uint8_t index,
290 			    uint8_t mask, uint8_t val);
291 uint8_t ast_get_index_reg(struct ast_private *ast,
292 			  uint32_t base, uint8_t index);
293 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
294 			       uint32_t base, uint8_t index, uint8_t mask);
295 
ast_open_key(struct ast_private * ast)296 static inline void ast_open_key(struct ast_private *ast)
297 {
298 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
299 }
300 
301 #define AST_VIDMEM_SIZE_8M    0x00800000
302 #define AST_VIDMEM_SIZE_16M   0x01000000
303 #define AST_VIDMEM_SIZE_32M   0x02000000
304 #define AST_VIDMEM_SIZE_64M   0x04000000
305 #define AST_VIDMEM_SIZE_128M  0x08000000
306 
307 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
308 
309 struct ast_vbios_stdtable {
310 	u8 misc;
311 	u8 seq[4];
312 	u8 crtc[25];
313 	u8 ar[20];
314 	u8 gr[9];
315 };
316 
317 struct ast_vbios_enhtable {
318 	u32 ht;
319 	u32 hde;
320 	u32 hfp;
321 	u32 hsync;
322 	u32 vt;
323 	u32 vde;
324 	u32 vfp;
325 	u32 vsync;
326 	u32 dclk_index;
327 	u32 flags;
328 	u32 refresh_rate;
329 	u32 refresh_rate_index;
330 	u32 mode_id;
331 };
332 
333 struct ast_vbios_dclk_info {
334 	u8 param1;
335 	u8 param2;
336 	u8 param3;
337 };
338 
339 struct ast_vbios_mode_info {
340 	const struct ast_vbios_stdtable *std_table;
341 	const struct ast_vbios_enhtable *enh_table;
342 };
343 
344 struct ast_crtc_state {
345 	struct drm_crtc_state base;
346 
347 	/* Last known format of primary plane */
348 	const struct drm_format_info *format;
349 
350 	struct ast_vbios_mode_info vbios_mode_info;
351 };
352 
353 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
354 
355 int ast_mode_config_init(struct ast_private *ast);
356 
357 #define AST_MM_ALIGN_SHIFT 4
358 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
359 
360 #define AST_DP501_FW_VERSION_MASK	GENMASK(7, 4)
361 #define AST_DP501_FW_VERSION_1		BIT(4)
362 #define AST_DP501_PNP_CONNECTED		BIT(1)
363 
364 #define AST_DP501_DEFAULT_DCLK	65
365 
366 #define AST_DP501_GBL_VERSION	0xf000
367 #define AST_DP501_PNPMONITOR	0xf010
368 #define AST_DP501_LINKRATE	0xf014
369 #define AST_DP501_EDID_DATA	0xf020
370 
371 /* Define for Soc scratched reg */
372 #define COPROCESSOR_LAUNCH			BIT(5)
373 
374 /*
375  * Display Transmitter Type:
376  */
377 #define TX_TYPE_MASK				GENMASK(3, 1)
378 #define NO_TX						(0 << 1)
379 #define ITE66121_VBIOS_TX			(1 << 1)
380 #define SI164_VBIOS_TX				(2 << 1)
381 #define CH7003_VBIOS_TX			(3 << 1)
382 #define DP501_VBIOS_TX				(4 << 1)
383 #define ANX9807_VBIOS_TX			(5 << 1)
384 #define TX_FW_EMBEDDED_FW_TX		(6 << 1)
385 #define ASTDP_DPMCU_TX				(7 << 1)
386 
387 #define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
388 //#define AST_VRAM_INIT_BY_BMC		BIT(7)
389 //#define AST_VRAM_INIT_READY		BIT(6)
390 
391 /* Define for Soc scratched reg used on ASTDP */
392 #define AST_DP_PHY_SLEEP			BIT(4)
393 #define AST_DP_VIDEO_ENABLE		BIT(0)
394 
395 #define AST_DP_POWER_ON			true
396 #define AST_DP_POWER_OFF			false
397 
398 /*
399  * CRD1[b5]: DP MCU FW is executing
400  * CRDC[b0]: DP link success
401  * CRDF[b0]: DP HPD
402  * CRE5[b0]: Host reading EDID process is done
403  */
404 #define ASTDP_MCU_FW_EXECUTING			BIT(5)
405 #define ASTDP_LINK_SUCCESS				BIT(0)
406 #define ASTDP_HPD						BIT(0)
407 #define ASTDP_HOST_EDID_READ_DONE		BIT(0)
408 #define ASTDP_HOST_EDID_READ_DONE_MASK	GENMASK(0, 0)
409 
410 /*
411  * CRB8[b1]: Enable VSYNC off
412  * CRB8[b0]: Enable HSYNC off
413  */
414 #define AST_DPMS_VSYNC_OFF				BIT(1)
415 #define AST_DPMS_HSYNC_OFF				BIT(0)
416 
417 /*
418  * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
419  * Precondition:	A. ~AST_DP_PHY_SLEEP  &&
420  *			B. DP_HPD &&
421  *			C. DP_LINK_SUCCESS
422  */
423 #define ASTDP_MIRROR_VIDEO_ENABLE		BIT(4)
424 
425 #define ASTDP_EDID_READ_POINTER_MASK	GENMASK(7, 0)
426 #define ASTDP_EDID_VALID_FLAG_MASK		GENMASK(0, 0)
427 #define ASTDP_EDID_READ_DATA_MASK		GENMASK(7, 0)
428 
429 /*
430  * ASTDP setmode registers:
431  * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
432  * CRE1[7:0]: MISC1 (default: 0x00)
433  * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
434  */
435 #define ASTDP_MISC0_24bpp			BIT(5)
436 #define ASTDP_MISC1				0
437 #define ASTDP_AND_CLEAR_MASK		0x00
438 
439 /*
440  * ASTDP resoultion table:
441  * EX:	ASTDP_A_B_C:
442  *		A: Resolution
443  *		B: Refresh Rate
444  *		C: Misc information, such as CVT, Reduce Blanked
445  */
446 #define ASTDP_640x480_60		0x00
447 #define ASTDP_640x480_72		0x01
448 #define ASTDP_640x480_75		0x02
449 #define ASTDP_640x480_85		0x03
450 #define ASTDP_800x600_56		0x04
451 #define ASTDP_800x600_60		0x05
452 #define ASTDP_800x600_72		0x06
453 #define ASTDP_800x600_75		0x07
454 #define ASTDP_800x600_85		0x08
455 #define ASTDP_1024x768_60		0x09
456 #define ASTDP_1024x768_70		0x0A
457 #define ASTDP_1024x768_75		0x0B
458 #define ASTDP_1024x768_85		0x0C
459 #define ASTDP_1280x1024_60		0x0D
460 #define ASTDP_1280x1024_75		0x0E
461 #define ASTDP_1280x1024_85		0x0F
462 #define ASTDP_1600x1200_60		0x10
463 #define ASTDP_320x240_60		0x11
464 #define ASTDP_400x300_60		0x12
465 #define ASTDP_512x384_60		0x13
466 #define ASTDP_1920x1200_60		0x14
467 #define ASTDP_1920x1080_60		0x15
468 #define ASTDP_1280x800_60		0x16
469 #define ASTDP_1280x800_60_RB	0x17
470 #define ASTDP_1440x900_60		0x18
471 #define ASTDP_1440x900_60_RB	0x19
472 #define ASTDP_1680x1050_60		0x1A
473 #define ASTDP_1680x1050_60_RB	0x1B
474 #define ASTDP_1600x900_60		0x1C
475 #define ASTDP_1600x900_60_RB	0x1D
476 #define ASTDP_1366x768_60		0x1E
477 #define ASTDP_1152x864_75		0x1F
478 
479 int ast_mm_init(struct ast_private *ast);
480 
481 /* ast post */
482 void ast_enable_vga(struct drm_device *dev);
483 void ast_enable_mmio(struct drm_device *dev);
484 bool ast_is_vga_enabled(struct drm_device *dev);
485 void ast_post_gpu(struct drm_device *dev);
486 u32 ast_mindwm(struct ast_private *ast, u32 r);
487 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
488 void ast_patch_ahb_2500(struct ast_private *ast);
489 /* ast dp501 */
490 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
491 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
492 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
493 u8 ast_get_dp501_max_clk(struct drm_device *dev);
494 void ast_init_3rdtx(struct drm_device *dev);
495 
496 /* ast_i2c.c */
497 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
498 
499 /* aspeed DP */
500 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata);
501 void ast_dp_launch(struct drm_device *dev, u8 bPower);
502 void ast_dp_power_on_off(struct drm_device *dev, bool no);
503 void ast_dp_set_on_off(struct drm_device *dev, bool no);
504 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode);
505 
506 #endif
507