1 /****************************************************************************** 2 * Filename: hw_aux_wuc_h 3 * Revised: 2015-11-12 13:07:02 +0100 (Thu, 12 Nov 2015) 4 * Revision: 45056 5 * 6 * Copyright (c) 2015, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_WUC_H__ 38 #define __HW_AUX_WUC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_WUC component 44 // 45 //***************************************************************************** 46 // Module Clock Enable 47 #define AUX_WUC_O_MODCLKEN0 0x00000000 48 49 // Power Off Request 50 #define AUX_WUC_O_PWROFFREQ 0x00000004 51 52 // Power Down Request 53 #define AUX_WUC_O_PWRDWNREQ 0x00000008 54 55 // Power Down Acknowledgment 56 #define AUX_WUC_O_PWRDWNACK 0x0000000C 57 58 // Low Frequency Clock Request 59 #define AUX_WUC_O_CLKLFREQ 0x00000010 60 61 // Low Frequency Clock Acknowledgment 62 #define AUX_WUC_O_CLKLFACK 0x00000014 63 64 // Wake-up Event Flags 65 #define AUX_WUC_O_WUEVFLAGS 0x00000028 66 67 // Wake-up Event Clear 68 #define AUX_WUC_O_WUEVCLR 0x0000002C 69 70 // ADC Clock Control 71 #define AUX_WUC_O_ADCCLKCTL 0x00000030 72 73 // TDC Clock Control 74 #define AUX_WUC_O_TDCCLKCTL 0x00000034 75 76 // Reference Clock Control 77 #define AUX_WUC_O_REFCLKCTL 0x00000038 78 79 // Real Time Counter Sub Second Increment 0 80 #define AUX_WUC_O_RTCSUBSECINC0 0x0000003C 81 82 // Real Time Counter Sub Second Increment 1 83 #define AUX_WUC_O_RTCSUBSECINC1 0x00000040 84 85 // Real Time Counter Sub Second Increment Control 86 #define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 87 88 // MCU Bus Control 89 #define AUX_WUC_O_MCUBUSCTL 0x00000048 90 91 // MCU Bus Status 92 #define AUX_WUC_O_MCUBUSSTAT 0x0000004C 93 94 // AON Domain Control Status 95 #define AUX_WUC_O_AONCTLSTAT 0x00000050 96 97 // AUX Input Output Latch 98 #define AUX_WUC_O_AUXIOLATCH 0x00000054 99 100 // Module Clock Enable 1 101 #define AUX_WUC_O_MODCLKEN1 0x0000005C 102 103 //***************************************************************************** 104 // 105 // Register: AUX_WUC_O_MODCLKEN0 106 // 107 //***************************************************************************** 108 // Field: [7] AUX_ADI4 109 // 110 // Enables (1) or disables (0) clock for AUX_ADI4. 111 // ENUMs: 112 // EN System CPU has requested clock for AUX_ADI4 113 // DIS System CPU has not requested clock for AUX_ADI4 114 #define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 115 #define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 116 #define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 117 #define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 118 #define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 119 #define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 120 121 // Field: [6] AUX_DDI0_OSC 122 // 123 // Enables (1) or disables (0) clock for AUX_DDI0_OSC. 124 // ENUMs: 125 // EN System CPU has requested clock for AUX_DDI0_OSC 126 // DIS System CPU has not requested clock for 127 // AUX_DDI0_OSC 128 #define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 129 #define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 130 #define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 131 #define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 132 #define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 133 #define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 134 135 // Field: [5] TDC 136 // 137 // Enables (1) or disables (0) clock for AUX_TDCIF. 138 // 139 // Note that the TDC counter and reference clock sources must be requested 140 // separately using TDCCLKCTL and REFCLKCTL, respectively. 141 // ENUMs: 142 // EN System CPU has requested clock for TDC 143 // DIS System CPU has not requested clock for TDC 144 #define AUX_WUC_MODCLKEN0_TDC 0x00000020 145 #define AUX_WUC_MODCLKEN0_TDC_BITN 5 146 #define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 147 #define AUX_WUC_MODCLKEN0_TDC_S 5 148 #define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 149 #define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 150 151 // Field: [4] ANAIF 152 // 153 // Enables (1) or disables (0) clock for AUX_ANAIF. 154 // 155 // Note that the ADC internal clock must be requested separately using 156 // ADCCLKCTL. 157 // ENUMs: 158 // EN System CPU has requested clock for ANAIF 159 // DIS System CPU has not requested clock for ANAIF 160 #define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 161 #define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 162 #define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 163 #define AUX_WUC_MODCLKEN0_ANAIF_S 4 164 #define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 165 #define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 166 167 // Field: [3] TIMER 168 // 169 // Enables (1) or disables (0) clock for AUX_TIMER. 170 // ENUMs: 171 // EN System CPU has requested clock for TIMER 172 // DIS System CPU has not requested clock for TIMER 173 #define AUX_WUC_MODCLKEN0_TIMER 0x00000008 174 #define AUX_WUC_MODCLKEN0_TIMER_BITN 3 175 #define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 176 #define AUX_WUC_MODCLKEN0_TIMER_S 3 177 #define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 178 #define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 179 180 // Field: [2] AIODIO1 181 // 182 // Enables (1) or disables (0) clock for AUX_AIODIO1. 183 // ENUMs: 184 // EN System CPU has requested clock for AIODIO1 185 // DIS System CPU has not requested clock for AIODIO1 186 #define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 187 #define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 188 #define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 189 #define AUX_WUC_MODCLKEN0_AIODIO1_S 2 190 #define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 191 #define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 192 193 // Field: [1] AIODIO0 194 // 195 // Enables (1) or disables (0) clock for AUX_AIODIO0. 196 // ENUMs: 197 // EN System CPU has requested clock for AIODIO0 198 // DIS System CPU has not requested clock for AIODIO0 199 #define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 200 #define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 201 #define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 202 #define AUX_WUC_MODCLKEN0_AIODIO0_S 1 203 #define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 204 #define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 205 206 // Field: [0] SMPH 207 // 208 // Enables (1) or disables (0) clock for AUX_SMPH. 209 // ENUMs: 210 // EN System CPU has requested clock for SMPH 211 // DIS System CPU has not requested clock for SMPH 212 #define AUX_WUC_MODCLKEN0_SMPH 0x00000001 213 #define AUX_WUC_MODCLKEN0_SMPH_BITN 0 214 #define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 215 #define AUX_WUC_MODCLKEN0_SMPH_S 0 216 #define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 217 #define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 218 219 //***************************************************************************** 220 // 221 // Register: AUX_WUC_O_PWROFFREQ 222 // 223 //***************************************************************************** 224 // Field: [0] REQ 225 // 226 // Power off request 227 // 228 // 0: No action 229 // 1: Request to power down AUX. Once set, this bit shall not be cleared. The 230 // bit will be reset again when AUX is powered up again. 231 // 232 // The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and 233 // MCUBUSSTAT.DISCONNECTED=1. 234 #define AUX_WUC_PWROFFREQ_REQ 0x00000001 235 #define AUX_WUC_PWROFFREQ_REQ_BITN 0 236 #define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 237 #define AUX_WUC_PWROFFREQ_REQ_S 0 238 239 //***************************************************************************** 240 // 241 // Register: AUX_WUC_O_PWRDWNREQ 242 // 243 //***************************************************************************** 244 // Field: [0] REQ 245 // 246 // Power down request 247 // 248 // 0: Request for system to be in active mode 249 // 1: Request for system to be in power down mode 250 // 251 // When REQ is 1 one shall assume that the system is in power down, and that 252 // current supply is limited. When setting REQ = 0, one shall assume that the 253 // system is in power down until PWRDWNACK.ACK = 0 254 #define AUX_WUC_PWRDWNREQ_REQ 0x00000001 255 #define AUX_WUC_PWRDWNREQ_REQ_BITN 0 256 #define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 257 #define AUX_WUC_PWRDWNREQ_REQ_S 0 258 259 //***************************************************************************** 260 // 261 // Register: AUX_WUC_O_PWRDWNACK 262 // 263 //***************************************************************************** 264 // Field: [0] ACK 265 // 266 // Power down acknowledgment. Indicates whether the power down request given by 267 // PWRDWNREQ.REQ is captured by the AON domain or not 268 // 269 // 0: AUX can assume that the system is in active mode 270 // 1: The request for power down is acknowledged and the AUX must act like the 271 // system is in power down mode and power supply is limited 272 // 273 // The system CPU cannot use this bit since the bus bridge between MCU domain 274 // and AUX domain is always disconnected when this bit is set. For AUX_SCE use 275 // only 276 #define AUX_WUC_PWRDWNACK_ACK 0x00000001 277 #define AUX_WUC_PWRDWNACK_ACK_BITN 0 278 #define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 279 #define AUX_WUC_PWRDWNACK_ACK_S 0 280 281 //***************************************************************************** 282 // 283 // Register: AUX_WUC_O_CLKLFREQ 284 // 285 //***************************************************************************** 286 // Field: [0] REQ 287 // 288 // Low frequency request 289 // 290 // 0: Request clock frequency to be controlled by AON_WUC:AUXCLK and the system 291 // state 292 // 1: Request low frequency clock SCLK_LF as the clock source for AUX 293 // 294 // This bit must not be modified unless CLKLFACK.ACK matches the current value 295 #define AUX_WUC_CLKLFREQ_REQ 0x00000001 296 #define AUX_WUC_CLKLFREQ_REQ_BITN 0 297 #define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 298 #define AUX_WUC_CLKLFREQ_REQ_S 0 299 300 //***************************************************************************** 301 // 302 // Register: AUX_WUC_O_CLKLFACK 303 // 304 //***************************************************************************** 305 // Field: [0] ACK 306 // 307 // Acknowledgment of CLKLFREQ.REQ 308 // 309 // 0: Acknowledgement that clock frequency is controlled by AON_WUC:AUXCLK and 310 // the system state 311 // 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source 312 // for AUX 313 #define AUX_WUC_CLKLFACK_ACK 0x00000001 314 #define AUX_WUC_CLKLFACK_ACK_BITN 0 315 #define AUX_WUC_CLKLFACK_ACK_M 0x00000001 316 #define AUX_WUC_CLKLFACK_ACK_S 0 317 318 //***************************************************************************** 319 // 320 // Register: AUX_WUC_O_WUEVFLAGS 321 // 322 //***************************************************************************** 323 // Field: [2] AON_RTC_CH2 324 // 325 // Indicates pending event from AON_RTC_CH2 compare. Note that this flag will 326 // be set whenever the AON_RTC_CH2 event happens, but that does not mean that 327 // this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for 328 // the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, 329 // AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. 330 #define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 331 #define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 332 #define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 333 #define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 334 335 // Field: [1] AON_SW 336 // 337 // Indicates pending event triggered by system CPU writing a 1 to 338 // AON_WUC:AUXCTL.SWEV. 339 #define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 340 #define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 341 #define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 342 #define AUX_WUC_WUEVFLAGS_AON_SW_S 1 343 344 // Field: [0] AON_PROG_WU 345 // 346 // Indicates pending event triggered by the sources selected in 347 // AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and 348 // AON_EVENT:AUXWUSEL.WU2_EV. 349 #define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 350 #define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 351 #define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 352 #define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 353 354 //***************************************************************************** 355 // 356 // Register: AUX_WUC_O_WUEVCLR 357 // 358 //***************************************************************************** 359 // Field: [2] AON_RTC_CH2 360 // 361 // Set to clear the WUEVFLAGS.AON_RTC_CH2 wake-up event. Note that if RTC 362 // channel 2 is also set as source for AON_PROG_WU this field can also clear 363 // WUEVFLAGS.AON_PROG_WU 364 // 365 // This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. 366 #define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 367 #define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 368 #define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 369 #define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 370 371 // Field: [1] AON_SW 372 // 373 // Set to clear the WUEVFLAGS.AON_SW wake-up event. 374 // 375 // This bit must remain set until WUEVFLAGS.AON_SW returns to 0. 376 #define AUX_WUC_WUEVCLR_AON_SW 0x00000002 377 #define AUX_WUC_WUEVCLR_AON_SW_BITN 1 378 #define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 379 #define AUX_WUC_WUEVCLR_AON_SW_S 1 380 381 // Field: [0] AON_PROG_WU 382 // 383 // Set to clear the WUEVFLAGS.AON_PROG_WU wake-up event. Note only if an IO 384 // event is selected as wake-up event, is it possible to use this field to 385 // clear the source. Other sources cannot be cleared using this field. 386 // 387 // The IO pin needs to be assigned to AUX in the IOC and the input enable for 388 // the pin needs to be set in AIODIO0 or AIODIO1 for this clearing to take 389 // effect. 390 // 391 // This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. 392 #define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 393 #define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 394 #define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 395 #define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 396 397 //***************************************************************************** 398 // 399 // Register: AUX_WUC_O_ADCCLKCTL 400 // 401 //***************************************************************************** 402 // Field: [1] ACK 403 // 404 // Acknowledges the last value written to REQ. 405 #define AUX_WUC_ADCCLKCTL_ACK 0x00000002 406 #define AUX_WUC_ADCCLKCTL_ACK_BITN 1 407 #define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 408 #define AUX_WUC_ADCCLKCTL_ACK_S 1 409 410 // Field: [0] REQ 411 // 412 // Enables(1) or disables (0) the ADC internal clock. 413 // 414 // This bit must not be modified unless ACK matches the current value. 415 #define AUX_WUC_ADCCLKCTL_REQ 0x00000001 416 #define AUX_WUC_ADCCLKCTL_REQ_BITN 0 417 #define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 418 #define AUX_WUC_ADCCLKCTL_REQ_S 0 419 420 //***************************************************************************** 421 // 422 // Register: AUX_WUC_O_TDCCLKCTL 423 // 424 //***************************************************************************** 425 // Field: [1] ACK 426 // 427 // Acknowledges the last value written to REQ. 428 #define AUX_WUC_TDCCLKCTL_ACK 0x00000002 429 #define AUX_WUC_TDCCLKCTL_ACK_BITN 1 430 #define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 431 #define AUX_WUC_TDCCLKCTL_ACK_S 1 432 433 // Field: [0] REQ 434 // 435 // Enables(1) or disables (0) the TDC counter clock source. 436 // 437 // This bit must not be modified unless ACK matches the current value. 438 #define AUX_WUC_TDCCLKCTL_REQ 0x00000001 439 #define AUX_WUC_TDCCLKCTL_REQ_BITN 0 440 #define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 441 #define AUX_WUC_TDCCLKCTL_REQ_S 0 442 443 //***************************************************************************** 444 // 445 // Register: AUX_WUC_O_REFCLKCTL 446 // 447 //***************************************************************************** 448 // Field: [1] ACK 449 // 450 // Acknowledges the last value written to REQ. 451 #define AUX_WUC_REFCLKCTL_ACK 0x00000002 452 #define AUX_WUC_REFCLKCTL_ACK_BITN 1 453 #define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 454 #define AUX_WUC_REFCLKCTL_ACK_S 1 455 456 // Field: [0] REQ 457 // 458 // Enables(1) or disables (0) the TDC reference clock source. 459 // 460 // This bit must not be modified unless ACK matches the current value. 461 #define AUX_WUC_REFCLKCTL_REQ 0x00000001 462 #define AUX_WUC_REFCLKCTL_REQ_BITN 0 463 #define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 464 #define AUX_WUC_REFCLKCTL_REQ_S 0 465 466 //***************************************************************************** 467 // 468 // Register: AUX_WUC_O_RTCSUBSECINC0 469 // 470 //***************************************************************************** 471 // Field: [15:0] INC15_0 472 // 473 // Bits 15:0 of the RTC sub-second increment value. 474 #define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 475 #define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF 476 #define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 477 478 //***************************************************************************** 479 // 480 // Register: AUX_WUC_O_RTCSUBSECINC1 481 // 482 //***************************************************************************** 483 // Field: [7:0] INC23_16 484 // 485 // Bits 23:16 of the RTC sub-second increment value. 486 #define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 487 #define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF 488 #define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 489 490 //***************************************************************************** 491 // 492 // Register: AUX_WUC_O_RTCSUBSECINCCTL 493 // 494 //***************************************************************************** 495 // Field: [1] UPD_ACK 496 // 497 // Acknowledgment of the UPD_REQ. 498 #define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 499 #define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 500 #define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 501 #define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 502 503 // Field: [0] UPD_REQ 504 // 505 // Signal that a new real time counter sub second increment value is available 506 // 507 // 0: New sub second increment is not available 508 // 1: New sub second increment is available 509 // 510 // This bit must not be modified unless UPD_ACK matches the current value. 511 #define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 512 #define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 513 #define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 514 #define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 515 516 //***************************************************************************** 517 // 518 // Register: AUX_WUC_O_MCUBUSCTL 519 // 520 //***************************************************************************** 521 // Field: [0] DISCONNECT_REQ 522 // 523 // Requests the AUX domain bus to be disconnected from the MCU domain bus. The 524 // request has no effect when AON_WUC:AUX_CTL.AUX_FORCE_ON is set. 525 // 526 // The disconnection status can be monitored through MCUBUSSTAT. Note however 527 // that this register cannot be read by the system CPU while disconnected. 528 // 529 // It is recommended that this bit is set and remains set after initial 530 // power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to 531 // connect/disconnect the bus. 532 #define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 533 #define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 534 #define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 535 #define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 536 537 //***************************************************************************** 538 // 539 // Register: AUX_WUC_O_MCUBUSSTAT 540 // 541 //***************************************************************************** 542 // Field: [1] DISCONNECTED 543 // 544 // Indicates whether the AUX domain and MCU domain buses are currently 545 // disconnected (1) or connected (0). 546 #define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 547 #define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 548 #define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 549 #define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 550 551 // Field: [0] DISCONNECT_ACK 552 // 553 // Acknowledges reception of the bus disconnection request, by matching the 554 // value of MCUBUSCTL.DISCONNECT_REQ. 555 // 556 // Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain 557 // bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ 558 #define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 559 #define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 560 #define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 561 #define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 562 563 //***************************************************************************** 564 // 565 // Register: AUX_WUC_O_AONCTLSTAT 566 // 567 //***************************************************************************** 568 // Field: [1] AUX_FORCE_ON 569 // 570 // Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. 571 #define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 572 #define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 573 #define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 574 #define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 575 576 // Field: [0] SCE_RUN_EN 577 // 578 // Status of AON_WUC:AUX_CTL.SCE_RUN_EN. 579 #define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 580 #define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 581 #define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 582 #define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 583 584 //***************************************************************************** 585 // 586 // Register: AUX_WUC_O_AUXIOLATCH 587 // 588 //***************************************************************************** 589 // Field: [0] EN 590 // 591 // Opens (1) or closes (0) the AUX_AIODIO0/AUX_AIODIO1 signal latching. 592 // 593 // At startup, set EN = TRANSP before configuring AUX_AIODIO0/AUX_AIODIO1 and 594 // subsequently selecting AUX mode in the AON_IOC. 595 // 596 // When powering off the AUX domain (using PWROFFREQ.REQ), set EN = STATIC in 597 // advance preserve the current state (mode and output value) of the I/O pins. 598 // ENUMs: 599 // TRANSP Latches are transparent ( open ) 600 // STATIC Latches are static ( closed ) 601 #define AUX_WUC_AUXIOLATCH_EN 0x00000001 602 #define AUX_WUC_AUXIOLATCH_EN_BITN 0 603 #define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 604 #define AUX_WUC_AUXIOLATCH_EN_S 0 605 #define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 606 #define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 607 608 //***************************************************************************** 609 // 610 // Register: AUX_WUC_O_MODCLKEN1 611 // 612 //***************************************************************************** 613 // Field: [7] AUX_ADI4 614 // 615 // Enables (1) or disables (0) clock for AUX_ADI4. 616 // ENUMs: 617 // EN AUX_SCE has requested clock for AUX_ADI4 618 // DIS AUX_SCE has not requested clock for AUX_ADI4 619 #define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 620 #define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 621 #define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 622 #define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 623 #define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 624 #define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 625 626 // Field: [6] AUX_DDI0_OSC 627 // 628 // Enables (1) or disables (0) clock for AUX_DDI0_OSC. 629 // ENUMs: 630 // EN AUX_SCE has requested clock for AUX_DDI0_OSC 631 // DIS AUX_SCE has not requested clock for AUX_DDI0_OSC 632 #define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 633 #define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 634 #define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 635 #define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 636 #define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 637 #define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 638 639 // Field: [4] ANAIF 640 // 641 // Enables (1) or disables (0) clock for AUX_ANAIF. 642 // ENUMs: 643 // EN AUX_SCE has requested clock for ANAIF 644 // DIS AUX_SCE has not requested clock for ANAIF 645 #define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 646 #define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 647 #define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 648 #define AUX_WUC_MODCLKEN1_ANAIF_S 4 649 #define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 650 #define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 651 652 // Field: [3] TIMER 653 // 654 // Enables (1) or disables (0) clock for AUX_TIMER. 655 // ENUMs: 656 // EN AUX_SCE has requested clock for TIMER 657 // DIS AUX_SCE has not requested clock for TIMER 658 #define AUX_WUC_MODCLKEN1_TIMER 0x00000008 659 #define AUX_WUC_MODCLKEN1_TIMER_BITN 3 660 #define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 661 #define AUX_WUC_MODCLKEN1_TIMER_S 3 662 #define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 663 #define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 664 665 // Field: [2] AIODIO1 666 // 667 // Enables (1) or disables (0) clock for AUX_AIODIO1. 668 // ENUMs: 669 // EN AUX_SCE has requested clock for AIODIO1 670 // DIS AUX_SCE has not requested clock for AIODIO1 671 #define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 672 #define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 673 #define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 674 #define AUX_WUC_MODCLKEN1_AIODIO1_S 2 675 #define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 676 #define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 677 678 // Field: [1] AIODIO0 679 // 680 // Enables (1) or disables (0) clock for AUX_AIODIO0. 681 // ENUMs: 682 // EN AUX_SCE has requested clock for AIODIO0 683 // DIS AUX_SCE has not requested clock for AIODIO0 684 #define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 685 #define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 686 #define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 687 #define AUX_WUC_MODCLKEN1_AIODIO0_S 1 688 #define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 689 #define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 690 691 // Field: [0] SMPH 692 // 693 // Enables (1) or disables (0) clock for AUX_SMPH. 694 // ENUMs: 695 // EN AUX_SCE has requested clock for SMPH 696 // DIS AUX_SCE has not requested clock for SMPH 697 #define AUX_WUC_MODCLKEN1_SMPH 0x00000001 698 #define AUX_WUC_MODCLKEN1_SMPH_BITN 0 699 #define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 700 #define AUX_WUC_MODCLKEN1_SMPH_S 0 701 #define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 702 #define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 703 704 705 #endif // __AUX_WUC__ 706