1 /** 2 ****************************************************************************** 3 * @file rtl8721d_adc.h 4 * @author 5 * @version V1.0.0 6 * @date 2016-05-17 7 * @brief This file contains all the functions prototypes for the ADC firmware 8 * library. 9 ****************************************************************************** 10 * @attention 11 * 12 * This module is a confidential and proprietary property of RealTek and 13 * possession or use of this module requires written permission of RealTek. 14 * 15 * Copyright(c) 2016, Realtek Semiconductor Corporation. All rights reserved. 16 ****************************************************************************** 17 */ 18 19 #ifndef _RTL8721D_ADC_H_ 20 #define _RTL8721D_ADC_H_ 21 22 /** @addtogroup AmebaD_Periph_Driver 23 * @{ 24 */ 25 26 /** @defgroup ADC 27 * @brief ADC driver modules 28 * @{ 29 */ 30 31 /** @addtogroup ADC 32 * @verbatim 33 ***************************************************************************************** 34 * Introduction 35 ***************************************************************************************** 36 * ADC: 37 * - Base Address: ADC 38 * - Channel number: 11 39 * - CH8~10: internal ADC channel 40 * - CH0~7: external ADC channel 41 * - Sample rate: configurable, frequency = CLK_ADC_CORE/divider, in which CLK_ADC_CORE is 2MHz, and can 42 * be divided by 12/16/32/64. 43 * - Resolution: 12 bit 44 * - Analog signal sampling: support 0 ~ 3.3V 45 * - IRQ: ADC_IRQ 46 * - Support Software-Trigger mode, Automatic mode, Timer-Trigger mode and Comparator-Assist mode. 47 * - GDMA source handshake interface: GDMA_HANDSHAKE_INTERFACE_ADC_RX 48 * 49 ***************************************************************************************** 50 * How to use ADC in interrupt mode 51 ***************************************************************************************** 52 * To use ADC in interrupt mode, the following steps are mandatory: 53 * 54 * 1. Enable the ADC interface clock: 55 * RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE); 56 * 57 * 2. Fill the ADC_InitStruct with the desired parameters. 58 * 59 * 3. Init Hardware with the parameters in ADC_InitStruct. 60 * ADC_Init(ADC_InitTypeDef* ADC_InitStruct) 61 * 62 * 4. Clear ADC interrupt: 63 * ADC_INTClear() 64 * 65 * 5. To configure interrupts: 66 * ADC_INTConfig(ADC_IT, ENABLE) 67 * 68 * 6. Enable the NVIC and the corresponding interrupt using following function. 69 * -InterruptRegister(): register the ADC irq handler 70 * -InterruptEn(): Enable the NVIC interrupt and set irq priority 71 * 72 * 7. Activate the ADC: 73 * ADC_Cmd(ENABLE). 74 * 75 * 8. Enbale specified mode: 76 * ADC_SWTrigCmd(ENABLE)/ADC_AutoCSwCmd(ENABLE)/ADC_TimerTrigCmd(Tim_Idx, PeriodMs, ENABLE) 77 * 78 * @note 1. If use ADC compare mode, call ADC_SetComp(ADC_channel, CompThresH, CompThresL, CompCtrl) to configure 79 * 2. If use ADC comparator-assist mode, you need to setup and enable comparator. 80 * 81 ***************************************************************************************** 82 * How to use ADC in DMA mode 83 ***************************************************************************************** 84 * To use ADC in DMA mode, the following steps are mandatory: 85 * 86 * 1. Enable the ADC interface clock: 87 * RCC_PeriphClockCmd(APBPeriph_ADC, APBPeriph_ADC_CLOCK, ENABLE); 88 * 89 * 2. Fill the ADC_InitStruct with the desired parameters. 90 * 91 * 3. Init Hardware use step2 parameters. 92 * ADC_Init(ADC_InitTypeDef* ADC_InitStruct). 93 * 94 * 4. Enable DMA read mode. 95 * ADC_SetDmaEnable(). 96 * 97 * 5. Init and Enable ADC RX GDMA, configure GDMA related configurations(source address/destination address/block size etc.) 98 * ADC_RXGDMA_Init(). 99 * 100 * 6. Activate the ADC peripheral: 101 * ADC_Cmd(ENABLE). 102 * 103 * 7. Enbale specified mode: 104 * ADC_SWTrigCmd(ENABLE)/ADC_AutoCSwCmd(ENABLE)/ \ 105 * ADC_TimerTrigCmd(Tim_Idx, PeriodMs, ENABLE) 106 * 107 ***************************************************************************************** 108 * @endverbatim 109 */ 110 111 /* Exported types ------------------------------------------------------------*/ 112 113 /** @defgroup ADC_Exported_Types ADC Exported Types 114 * @{ 115 */ 116 117 /** 118 * @brief ADC Init structure definition 119 */ 120 typedef struct { 121 u8 ADC_OpMode; /*!< Specifies ADC operation mode. 122 This parameter can be a value of @ref ADC_Operation_Mode_Definitions */ 123 124 u8 ADC_CvlistLen; /*!< The number of valid items in the ADC conversion channel list is (ADC_CvlistLen + 1). 125 This parameter can be set to 0~15 */ 126 127 u8 ADC_Cvlist[16]; /*!< Specifies the ADC channel conversion order. Each member should be 128 the channel index */ 129 130 u8 ADC_ClkDiv; /*!< Specifies ADC clock divider. 131 This parameter can be a value of @ref ADC_CLK_Divider_Definitions */ 132 133 u8 ADC_RxThresholdLevel; /*!< Specifies the receive FIFO threshold level. 134 When the number of rx FIFO entries is greater than or equal to this 135 value +1, the receive FIFO full interrupt is triggered. */ 136 137 u8 ADC_DMAThresholdLevel; /*!< Specifies ADC DMA operation threshold. 138 The dma_rx_req is generated when the number of valid data entries in the 139 receive FIFO is equal to or above this field value+1 and ADC_DMA_EN=1. */ 140 141 u8 ADC_SpecialCh; /*!< Specifies ADC particular channel. This parameter defines that ADC module 142 should send interrupt signal to system when a conversion which of channel 143 number is the same as this parameter. Default 0xFF means there is no need 144 to set particular channel. */ 145 146 u32 ADC_ChanInType; /*!< Specifies CH0~5 input type. Default all channels are in single-end mode. 147 If some channels need to be set to differential mode, use a value or 148 combination of @ref ADC_CH_Input_Type_Definitions. */ 149 150 u8 ADC_ChIDEn; /*!< Specifies whether ADC enables BIT_ADC_DAT_CHID or not. */ 151 152 } ADC_InitTypeDef; 153 /** 154 * @} 155 */ 156 157 158 /* Exported constants --------------------------------------------------------*/ 159 160 /** @defgroup ADC_Exported_Constants ADC Exported Constants 161 * @{ 162 */ 163 164 /** @defgroup ADC_Chn_Selection 165 * @{ 166 */ 167 #define ADC_CH0 ((u8)0x00) 168 #define ADC_CH1 ((u8)0x01) 169 #define ADC_CH2 ((u8)0x02) 170 #define ADC_CH3 ((u8)0x03) 171 #define ADC_CH4 ((u8)0x04) 172 #define ADC_CH5 ((u8)0x05) 173 #define ADC_CH6 ((u8)0x06) 174 #define ADC_CH7 ((u8)0x07) 175 #define ADC_CH8 ((u8)0x08) /*!< ADC internal channel */ 176 #define ADC_CH9 ((u8)0x09) /*!< ADC internal channel */ 177 #define ADC_CH10 ((u8)0x0a) /*!< ADC internal channel */ 178 #define ADC_CH_NUM (11) 179 #define ADC_GLOBAL ((u8)0xFF) 180 181 #define IS_ADC_CHN_SEL(SEL) (((SEL) == ADC_CH0) || \ 182 ((SEL) == ADC_CH1) || \ 183 ((SEL) == ADC_CH2) || \ 184 ((SEL) == ADC_CH3) || \ 185 ((SEL) == ADC_CH4) || \ 186 ((SEL) == ADC_CH5) || \ 187 ((SEL) == ADC_CH6) || \ 188 ((SEL) == ADC_CH7) || \ 189 ((SEL) == ADC_CH8) || \ 190 ((SEL) == ADC_CH9) || \ 191 ((SEL) == ADC_CH10)) 192 193 /** 194 * @} 195 */ 196 197 198 /** @defgroup ADC_CLK_Divider_Definitions 199 * @{ 200 */ 201 #define ADC_CLK_DIV_12 ((u8)0x00) 202 #define ADC_CLK_DIV_16 ((u8)0x01) 203 #define ADC_CLK_DIV_32 ((u8)0x02) 204 #define ADC_CLK_DIV_64 ((u8)0x03) 205 206 #define IS_ADC_SAMPLE_CLK(CLK) (((CLK) == ADC_CLK_DIV_12) || \ 207 ((CLK) == ADC_CLK_DIV_16) || \ 208 ((CLK) == ADC_CLK_DIV_32) || \ 209 ((CLK) == ADC_CLK_DIV_64)) 210 211 /** 212 * @} 213 */ 214 215 216 /** @defgroup ADC_Operation_Mode_Definitions 217 * @{ 218 */ 219 #define ADC_SW_TRI_MODE ((u8)0x00) /*!< ADC software-trigger mode */ 220 #define ADC_AUTO_MODE ((u8)0x01) /*!< ADC automatic mode */ 221 #define ADC_TIM_TRI_MODE ((u8)0x02) /*!< ADC timer-trigger mode */ 222 #define ADC_COMP_ASSIST_MODE ((u8)0x03) /*!< ADC comparator-assist mode */ 223 224 #define IS_ADC_MODE(mode) (((mode) == ADC_SW_TRI_MODE) || \ 225 ((mode) == ADC_AUTO_MODE) || \ 226 ((mode) == ADC_TIM_TRI_MODE) || \ 227 ((mode) == ADC_COMP_ASSIST_MODE)) 228 229 /** 230 * @} 231 */ 232 233 234 /** @defgroup ADC_CH_Input_Type_Definitions 235 * @{ 236 */ 237 #define ADC_DIFFERENTIAL_CH(x) BIT(x) 238 239 /** 240 * @} 241 */ 242 243 /** @defgroup ADC_Compare_Control_Definitions 244 * @{ 245 */ 246 #define ADC_COMP_SMALLER_THAN_THL ((u8)0x00) /*!< Vin < ADC_COMP_TH_L */ 247 #define ADC_COMP_GREATER_THAN_THH ((u8)0x01) /*!< Vin > ADC_COMP_TH_H */ 248 #define ADC_COMP_WITHIN_THL_AND_THH ((u8)0x02) /*!< Vin >= ADC_COMP_TH_L && Vin <= ADC_COMP_TH_H */ 249 #define ADC_COMP_OUTSIDE_THL_AND_THH ((u8)0x03) /*!< Vin < ADC_COMP_TH_L || Vin > ADC_COMP_TH_H */ 250 #define IS_ADC_COMP_CRITERIA(rule) (((rule) == ADC_COMP_SMALLER_THAN_THL) || \ 251 ((rule) == ADC_COMP_GREATER_THAN_THH) || \ 252 ((rule) == ADC_COMP_WITHIN_THL_AND_THH) || \ 253 ((rule) == ADC_COMP_OUTSIDE_THL_AND_THH)) 254 255 /** 256 * @} 257 */ 258 259 /** @defgroup ADC_Compare_Threshold_Definitions 260 * @{ 261 */ 262 #define IS_ADC_VALID_COMP_TH(x) (x < 0x1000) 263 264 /** 265 * @} 266 */ 267 268 /** @defgroup ADC_Timer_Definitions 269 * @{ 270 */ 271 #define IS_ADC_VALID_TIM(idx) (idx < 4) 272 273 /** 274 * @} 275 */ 276 277 278 /** 279 * @} 280 */ 281 282 /** @defgroup ADC_Exported_Functions ADC Exported Functions 283 * @{ 284 */ 285 _LONG_CALL_ void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); 286 _LONG_CALL_ void ADC_Init(ADC_InitTypeDef* ADC_InitStruct); 287 _LONG_CALL_ void ADC_Cmd(u32 NewState); 288 _LONG_CALL_ void ADC_INTConfig(u32 ADC_IT, u32 NewState); 289 _LONG_CALL_ void ADC_INTClear(void); 290 _LONG_CALL_ void ADC_INTClearPendingBits(u32 ADC_IT); 291 _LONG_CALL_ u32 ADC_GetISR(void); 292 _LONG_CALL_ u32 ADC_GetRawISR(void); 293 _LONG_CALL_ u32 ADC_GetCompStatus(u8 ADC_Channel); 294 _LONG_CALL_ u32 ADC_GetRxCount(void); 295 _LONG_CALL_ u32 ADC_GetLastChan(void); 296 _LONG_CALL_ void ADC_SetComp(u8 ADC_channel, u16 CompThresH, u16 CompThresL, u8 CompCtrl); 297 _LONG_CALL_ void ADC_ResetCSwList(void); 298 _LONG_CALL_ u32 ADC_Readable(void); 299 _LONG_CALL_ u16 ADC_Read(void); 300 _LONG_CALL_ void ADC_ReceiveBuf(u16 *pBuf, u32 len); 301 _LONG_CALL_ void ADC_ClearFIFO(void); 302 _LONG_CALL_ u32 ADC_GetStatus(void); 303 _LONG_CALL_ void ADC_SWTrigCmd(u32 NewState); 304 _LONG_CALL_ void ADC_AutoCSwCmd(u32 NewState); 305 _LONG_CALL_ void ADC_TimerTrigCmd(u8 Tim_Idx, u32 PeriodMs, u32 NewState); 306 _LONG_CALL_ void ADC_SetDmaEnable(u32 newState); 307 _LONG_CALL_ u32 ADC_RXGDMA_Init(GDMA_InitTypeDef *GDMA_InitStruct, void *CallbackData, IRQ_FUN CallbackFunc, u8* pDataBuf, u32 DataLen); 308 /** 309 * @} 310 */ 311 312 /* Registers Definitions --------------------------------------------------------*/ 313 /**************************************************************************//** 314 * @defgroup ADC_Register_Definitions ADC Register Definitions 315 * @{ 316 *****************************************************************************/ 317 318 /**************************************************************************//** 319 * @defgroup REG_ADC_CONF 320 * @{ 321 *****************************************************************************/ 322 #define BIT_ADC_ENABLE BIT(9) 323 #define BIT_SHIFT_CVLIST_LEN 4 324 #define BIT_MASK_CVLIST_LEN (u32)(0x0000000F << BIT_SHIFT_CVLIST_LEN) 325 #define BIT_SHIFT_OP_MODE 1 326 #define BIT_MASK_OP_MODE (u32)(0x00000007 << BIT_SHIFT_OP_MODE) 327 #define BIT_ADC_REF_IN_SEL BIT(0) 328 329 /** @} */ 330 331 /**************************************************************************//** 332 * @defgroup REG_ADC_IN_TYPE 333 * @{ 334 *****************************************************************************/ 335 #define BIT_SHIFT_IN_TYPE_CH(x) (x) 336 #define BIT_ADC_IN_TYPE_CH(x) BIT(x) 337 338 /** @} */ 339 340 /**************************************************************************//** 341 * @defgroup REG_ADC_COMP_TH_CH 342 * @{ 343 *****************************************************************************/ 344 #define BIT_SHIFT_COMP_TH_H 16 345 #define BIT_MASK_COMP_TH_H (u32)(0x00000FFF << BIT_SHIFT_COMP_TH_H) 346 #define BIT_SHIFT_COMP_TH_L 0 347 #define BIT_MASK_COMP_TH_L (u32)(0x00000FFF << BIT_SHIFT_COMP_TH_L) 348 349 /** @} */ 350 351 /**************************************************************************//** 352 * @defgroup REG_ADC_COMP_CTRL 353 * @{ 354 *****************************************************************************/ 355 #define BIT_SHIFT_COMP_CTRL_CH(x) (2*x) 356 #define BIT_MASK_COMP_CTRL_CH(x) (u32)(0x00000003 << BIT_SHIFT_COMP_CTRL_CH(x)) 357 358 /** @} */ 359 360 361 /**************************************************************************//** 362 * @defgroup REG_ADC_COMP_STS 363 * @{ 364 *****************************************************************************/ 365 #define BIT_SHIFT_COMP_STS_CH(x) (2*x) 366 #define BIT_MASK_COMP_STS_CH(x) (u32)(0x00000003 << BIT_SHIFT_COMP_STS_CH(x)) 367 368 /** @} */ 369 370 /**************************************************************************//** 371 * @defgroup REG_ADC_CHSW_LIST0 372 * @{ 373 *****************************************************************************/ 374 #define BIT_SHIFT_CHSW0(x) (4*x) 375 #define BIT_MASK_CHSW0(x) (u32)(0x0000000F << BIT_SHIFT_CHSW0(x)) 376 377 /** @} */ 378 379 /**************************************************************************//** 380 * @defgroup REG_ADC_CHSW_LIST1 381 * @{ 382 *****************************************************************************/ 383 #define BIT_SHIFT_CHSW1(x) (4*(x - 8)) 384 #define BIT_MASK_CHSW1(x) (u32)(0x0000000F << BIT_SHIFT_CHSW1) 385 386 /** @} */ 387 388 /**************************************************************************//** 389 * @defgroup REG_ADC_RST_LIST 390 * @{ 391 *****************************************************************************/ 392 #define BIT_ADC_RST_LIST BIT(0) 393 394 /** @} */ 395 396 /**************************************************************************//** 397 * @defgroup REG_ADC_AUTO_CSW_CTRL 398 * @{ 399 *****************************************************************************/ 400 #define BIT_ADC_AUTO_CSW_EN BIT(0) 401 402 /** @} */ 403 404 /**************************************************************************//** 405 * @defgroup REG_ADC_SW_TRIG 406 * @{ 407 *****************************************************************************/ 408 #define BIT_ADC_SW_TRIG BIT(0) 409 410 /** @} */ 411 412 /**************************************************************************//** 413 * @defgroup REG_ADC_LAST_CH 414 * @{ 415 *****************************************************************************/ 416 #define BIT_ADC_LAST_CH (u32)(0x0000000F) 417 418 /** @} */ 419 420 /**************************************************************************//** 421 * @defgroup REG_ADC_BUSY_STS 422 * @{ 423 *****************************************************************************/ 424 #define BIT_ADC_FIFO_EMPTY BIT(2) 425 #define BIT_ADC_FIFO_FULL_REAL BIT(1) 426 #define BIT_ADC_BUSY_STS BIT(0) 427 428 /** @} */ 429 430 /**************************************************************************//** 431 * @defgroup REG_ADC_INTR_CTRL 432 * @{ 433 *****************************************************************************/ 434 #define BIT_ADC_IT_COMP_CH_EN(x) BIT(8+x) 435 #define BIT_ADC_IT_COMP_CH10_EN BIT(18) 436 #define BIT_ADC_IT_COMP_CH9_EN BIT(17) 437 #define BIT_ADC_IT_COMP_CH8_EN BIT(16) 438 #define BIT_ADC_IT_COMP_CH7_EN BIT(15) 439 #define BIT_ADC_IT_COMP_CH6_EN BIT(14) 440 #define BIT_ADC_IT_COMP_CH5_EN BIT(13) 441 #define BIT_ADC_IT_COMP_CH4_EN BIT(12) 442 #define BIT_ADC_IT_COMP_CH3_EN BIT(11) 443 #define BIT_ADC_IT_COMP_CH2_EN BIT(10) 444 #define BIT_ADC_IT_COMP_CH1_EN BIT(9) 445 #define BIT_ADC_IT_COMP_CH0_EN BIT(8) 446 #define BIT_ADC_IT_ERR_EN BIT(7) 447 #define BIT_ADC_IT_DAT_OVW_EN BIT(6) 448 #define BIT_ADC_IT_FIFO_EMPTY_EN BIT(5) 449 #define BIT_ADC_IT_FIFO_OVER_EN BIT(4) 450 #define BIT_ADC_IT_FIFO_FULL_EN BIT(3) 451 #define BIT_ADC_IT_CHCV_END_EN BIT(2) 452 #define BIT_ADC_IT_CV_END_EN BIT(1) 453 #define BIT_ADC_IT_CVLIST_END_EN BIT(0) 454 455 /** @} */ 456 457 /**************************************************************************//** 458 * @defgroup REG_ADC_INTR_STS 459 * @{ 460 *****************************************************************************/ 461 #define BIT_ADC_IT_COMP_CH10_STS BIT(18) 462 #define BIT_ADC_IT_COMP_CH9_STS BIT(17) 463 #define BIT_ADC_IT_COMP_CH8_STS BIT(16) 464 #define BIT_ADC_IT_COMP_CH7_STS BIT(15) 465 #define BIT_ADC_IT_COMP_CH6_STS BIT(14) 466 #define BIT_ADC_IT_COMP_CH5_STS BIT(13) 467 #define BIT_ADC_IT_COMP_CH4_STS BIT(12) 468 #define BIT_ADC_IT_COMP_CH3_STS BIT(11) 469 #define BIT_ADC_IT_COMP_CH2_STS BIT(10) 470 #define BIT_ADC_IT_COMP_CH1_STS BIT(9) 471 #define BIT_ADC_IT_COMP_CH0_STS BIT(8) 472 #define BIT_ADC_IT_ERR_STS BIT(7) 473 #define BIT_ADC_IT_DAT_OVW_STS BIT(6) 474 #define BIT_ADC_IT_FIFO_EMPTY_STS BIT(5) 475 #define BIT_ADC_IT_FIFO_OVER_STS BIT(4) 476 #define BIT_ADC_IT_FIFO_FULL_STS BIT(3) 477 #define BIT_ADC_IT_CHCV_END_STS BIT(2) 478 #define BIT_ADC_IT_CV_END_STS BIT(1) 479 #define BIT_ADC_IT_CVLIST_END_STS BIT(0) 480 #define BIT_ADC_IT_COMP_ALL_STS ( BIT_ADC_IT_COMP_CH0_STS | \ 481 BIT_ADC_IT_COMP_CH1_STS | \ 482 BIT_ADC_IT_COMP_CH2_STS | \ 483 BIT_ADC_IT_COMP_CH3_STS | \ 484 BIT_ADC_IT_COMP_CH4_STS | \ 485 BIT_ADC_IT_COMP_CH5_STS | \ 486 BIT_ADC_IT_COMP_CH6_STS | \ 487 BIT_ADC_IT_COMP_CH7_STS | \ 488 BIT_ADC_IT_COMP_CH8_STS | \ 489 BIT_ADC_IT_COMP_CH9_STS | \ 490 BIT_ADC_IT_COMP_CH10_STS ) 491 #define BIT_ADC_IT_ALL_STS (BIT_ADC_IT_COMP_ALL_STS | \ 492 BIT_ADC_IT_ERR_STS | \ 493 BIT_ADC_IT_DAT_OVW_STS |\ 494 BIT_ADC_IT_FIFO_EMPTY_STS |\ 495 BIT_ADC_IT_FIFO_OVER_STS |\ 496 BIT_ADC_IT_FIFO_FULL_STS |\ 497 BIT_ADC_IT_CHCV_END_STS |\ 498 BIT_ADC_IT_CV_END_STS |\ 499 BIT_ADC_IT_CVLIST_END_STS) 500 501 /** @} */ 502 503 /**************************************************************************//** 504 * @defgroup REG_ADC_INTR_RAW_STS 505 * @{ 506 *****************************************************************************/ 507 #define BIT_ADC_IT_COMP_CH10_RAW_STS BIT(18) 508 #define BIT_ADC_IT_COMP_CH9_RAW_STS BIT(17) 509 #define BIT_ADC_IT_COMP_CH8_RAW_STS BIT(16) 510 #define BIT_ADC_IT_COMP_CH7_RAW_STS BIT(15) 511 #define BIT_ADC_IT_COMP_CH6_RAW_STS BIT(14) 512 #define BIT_ADC_IT_COMP_CH5_RAW_STS BIT(13) 513 #define BIT_ADC_IT_COMP_CH4_RAW_STS BIT(12) 514 #define BIT_ADC_IT_COMP_CH3_RAW_STS BIT(11) 515 #define BIT_ADC_IT_COMP_CH2_RAW_STS BIT(10) 516 #define BIT_ADC_IT_COMP_CH1_RAW_STS BIT(9) 517 #define BIT_ADC_IT_COMP_CH0_RAW_STS BIT(8) 518 #define BIT_ADC_IT_ERR_RAW_STS BIT(7) 519 #define BIT_ADC_IT_DAT_OVW_RAW_STS BIT(6) 520 #define BIT_ADC_IT_FIFO_EMPTY_RAW_STS BIT(5) 521 #define BIT_ADC_IT_FIFO_OVER_RAW_STS BIT(4) 522 #define BIT_ADC_IT_FIFO_FULL_RAW_STS BIT(3) 523 #define BIT_ADC_IT_CHCV_END_RAW_STS BIT(2) 524 #define BIT_ADC_IT_CV_END_RAW_STS BIT(1) 525 #define BIT_ADC_IT_CVLIST_END_RAW_STS BIT(0) 526 527 /** @} */ 528 529 530 /**************************************************************************//** 531 * @defgroup REG_ADC_IT_CHNO_CON 532 * @{ 533 *****************************************************************************/ 534 #define BIT_MASK_IT_CHNO_CON (u32)(0x0000000F) 535 536 /** @} */ 537 538 /**************************************************************************//** 539 * @defgroup REG_ADC_FULL_LVL 540 * @{ 541 *****************************************************************************/ 542 #define BIT_MASK_FULL_LVL (u32)(0x0000003F) 543 544 /** @} */ 545 546 /**************************************************************************//** 547 * @defgroup REG_ADC_ADC_EXT_TRIG_TIMER_SEL 548 * @{ 549 *****************************************************************************/ 550 #define BIT_MASK_EXT_TRIG_TIMER_SEL (u32)(0x00000007) 551 552 /** @} */ 553 554 /**************************************************************************//** 555 * @defgroup REG_ADC_DATA_CH0_to_CH11 556 * @{ 557 *****************************************************************************/ 558 #define BIT_ADC_DAT_RDY BIT(17) 559 #define BIT_ADC_DAT_OVW BIT(16) 560 #define BIT_MASK_DATA_CH (u32)(0x00000FFF) 561 562 /** @} */ 563 564 /**************************************************************************//** 565 * @defgroup REG_ADC_DATA_GLOBAL 566 * @{ 567 *****************************************************************************/ 568 #define BIT_MASK_DAT_CH (u32)(0x0000000F << 18) 569 #define BIT_MASK_DAT_CHID (u32)(0x0000000F << 12) 570 #define BIT_MASK_DAT_GLOBAL (u32)(0x00000FFF) 571 572 /** @} */ 573 574 /**************************************************************************//** 575 * @defgroup REG_ADC_DMA_CON 576 * @{ 577 *****************************************************************************/ 578 #define BIT_SHIFT_DMA_LVL 8 579 #define BIT_MASK_DMA_LVL (u32)(0x0000000F << BIT_SHIFT_DMA_LVL) 580 #define BIT_ADC_DMA_EN BIT(0) 581 582 /** @} */ 583 584 /**************************************************************************//** 585 * @defgroup REG_ADC_FLR 586 * @{ 587 *****************************************************************************/ 588 #define BIT_MASK_FLR (u32)(0x0000007F) 589 590 /** @} */ 591 592 /**************************************************************************//** 593 * @defgroup REG_ADC_CLR_FIFO 594 * @{ 595 *****************************************************************************/ 596 #define BIT_ADC_CLR_FIFO BIT(0) 597 598 /** @} */ 599 600 /**************************************************************************//** 601 * @defgroup REG_ADC_CLK_DIV 602 * @{ 603 *****************************************************************************/ 604 #define BIT_MASK_CLK_DIV (u32)(0x00000007) 605 606 /** @} */ 607 608 /**************************************************************************//** 609 * @defgroup REG_ADC_DELAY_CNT 610 * @{ 611 *****************************************************************************/ 612 #define BIT_ADC_DAT_CHID BIT(31) 613 #define BIT_ADC_DAT_DELAY (u32)(0x00000003 << 2) 614 #define BIT_ADC_CTRL_DELAY (u32)(0x00000003) 615 /** @} */ 616 617 /**************************************************************************//** 618 * @defgroup REG_ADC_PWR_CTRL 619 * @{ 620 *****************************************************************************/ 621 #define BIT_ADC_PWR_CTRL BIT(0) 622 623 /** @} */ 624 625 /** @} */ 626 627 /** 628 * @} 629 */ 630 631 /** 632 * @} 633 */ 634 635 /* Other Definitions --------------------------------------------------------*/ 636 637 638 #endif /* _RTL8721D_ADC_H_ */ 639 640 /******************* (C) COPYRIGHT 2016 Realtek Semiconductor *****END OF FILE****/ 641