1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017-2019 NXP 4 */ 5 #ifndef __IMX6_CRM_H__ 6 #define __IMX6_CRM_H__ 7 8 #define CCM_CCR 0x0000 9 #define CCM_CCDR 0x0004 10 #define CCM_CSR 0x0008 11 #define CCM_CCSR 0x000C 12 #define CCM_CACRR 0x0010 13 #define CCM_CBCDR 0x0014 14 #define CCM_CBCMR 0x0018 15 #define CCM_CSCMR1 0x001C 16 #define CCM_CSCMR2 0x0020 17 #define CCM_CSCDR1 0x0024 18 #define CCM_CS1CDR 0x0028 19 #define CCM_CS2CDR 0x002C 20 #define CCM_CDCDR 0x0030 21 #define CCM_CHSCCDR 0x0034 22 #define CCM_CSCDR2 0x0038 23 #define CCM_CSCDR3 0x003C 24 #define CCM_CSCDR4 0x0040 25 #define CCM_CWDR 0x0044 26 #define CCM_CDHIPR 0x0048 27 #define CCM_CDCR 0x004C 28 #define CCM_CTOR 0x0050 29 #define CCM_CLPCR 0x0054 30 #define CCM_CISR 0x0058 31 #define CCM_CIMR 0x005C 32 #define CCM_CCOSR 0x0060 33 #define CCM_CGPR 0x0064 34 #define CCM_CCGR0 0x0068 35 #define CCM_CCGR1 0x006C 36 #define CCM_CCGR2 0x0070 37 #define CCM_CCGR3 0x0074 38 #define CCM_CCGR4 0x0078 39 #define CCM_CCGR5 0x007C 40 #define CCM_CCGR6 0x0080 41 #define CCM_CCGR7 0x0084 42 #define CCM_CMEOR 0x0088 43 44 #define CCM_ANALOG_PLL_SYS 0x4000 45 #define CCM_ANALOG_PLL_SYS_SET 0x4004 46 #define CCM_ANALOG_PLL_SYS_CLR 0x4008 47 #define CCM_ANALOG_PLL_SYS_TOG 0x400C 48 #define CCM_ANALOG_USB1_PLL_480_CTRL 0x4010 49 #define CCM_ANALOG_USB1_PLL_480_CTRL_SET 0x4014 50 #define CCM_ANALOG_USB1_PLL_480_CTRL_CLR 0x4018 51 #define CCM_ANALOG_USB1_PLL_480_CTRL_TOG 0x401C 52 53 #define CCM_ANALOG_PLL_528 0x4030 54 #define CCM_ANALOG_PLL_528_SET 0x4034 55 #define CCM_ANALOG_PLL_528_CLR 0x4038 56 #define CCM_ANALOG_PLL_528_TOG 0x403C 57 #define CCM_ANALOG_PLL_528_SS 0x4040 58 #define CCM_ANALOG_PLL_528_NUM 0x4050 59 #define CCM_ANALOG_PLL_528_DENOM 0x4060 60 #define CCM_ANALOG_PLL_AUDIO 0x4070 61 #define CCM_ANALOG_PLL_AUDIO_SET 0x4074 62 #define CCM_ANALOG_PLL_AUDIO_CLR 0x4078 63 #define CCM_ANALOG_PLL_AUDIO_TOG 0x407C 64 #define CCM_ANALOG_PLL_AUDIO_NUM 0x4080 65 #define CCM_ANALOG_PLL_AUDIO_DENOM 0x4090 66 #define CCM_ANALOG_PLL_VIDEO 0x40A0 67 #define CCM_ANALOG_PLL_VIDEO_SET 0x40A4 68 #define CCM_ANALOG_PLL_VIDEO_CLR 0x40A8 69 #define CCM_ANALOG_PLL_VIDEO_TOG 0x40AC 70 #define CCM_ANALOG_PLL_VIDEO_NUM 0x40B0 71 #define CCM_ANALOG_PLL_VEDIO_DENON 0x40C0 72 #define CCM_ANALOG_PLL_ENET 0x40E0 73 #define CCM_ANALOG_PLL_ENET_SET 0x40E4 74 #define CCM_ANALOG_PLL_ENET_CLR 0x40E8 75 #define CCM_ANALOG_PLL_ENET_TOG 0x40EC 76 #define CCM_ANALOG_PFD_480 0x40F0 77 #define CCM_ANALOG_PFD_480_SET 0x40F4 78 #define CCM_ANALOG_PFD_480_CLR 0x40F8 79 #define CCM_ANALOG_PFD_480_TOG 0x40FC 80 #define CCM_ANALOG_PFD_528 0x4100 81 #define CCM_ANALOG_PFD_528_SET 0x4104 82 #define CCM_ANALOG_PFD_528_CLR 0x4108 83 #define CCM_ANALOG_PFD_528_TOG 0x410C 84 85 /* Define the bits in register CCR */ 86 #define BS_CCM_CCR_RBC_EN 27 87 #define BM_CCM_CCR_RBC_EN BIT32(BS_CCM_CCR_RBC_EN) 88 #define BS_CCM_CCR_REG_BYPASS_COUNT 21 89 #define BM_CCM_CCR_REG_BYPASS_COUNT \ 90 SHIFT_U32(0x3F, BS_CCM_CCR_REG_BYPASS_COUNT) 91 #define BS_CCM_CCR_WB_COUNT 16 92 #define BM_CCM_CCR_WB_COUNT SHIFT_U32(0x7, BS_CCM_CCR_WB_COUNT) 93 #define BS_CCM_CCR_OSCNT 0 94 #define BM_CCM_CCR_OSCNT SHIFT_U32(0xFF, BS_CCM_CCR_OSCNT) 95 #define CCM_CCR_COSC_EN SHIFT_U32((1 << 12), BS_CCM_CCR_OSCNT) 96 97 /* Define the bits in register CCDR */ 98 #define BS_CCM_CCDR_MMDC_CH1_HS_MASK 16 99 #define BM_CCM_CCDR_MMDC_CH1_HS_MASK BIT32(BS_CCM_CCDR_MMDC_CH1_HS_MASK) 100 #define BS_CCM_CCDR_MMDC_CH0_HS_MASK 17 101 #define BM_CCM_CCDR_MMDC_CH0_HS_MASK BIT32(BS_CCM_CCDR_MMDC_CH0_HS_MASK) 102 103 /* Define the bits in register CSR */ 104 #define BS_CCM_CSR_COSC_READY 5 105 #define BM_CCM_CSR_COSC_READY BIT32(BS_CCM_CSR_COSC_READY) 106 #define BS_CCM_CSR_REF_EN_B 0 107 #define BM_CCM_CSR_REF_EN_B BIT32(BS_CCM_CSR_REF_EN_B) 108 109 /* Define the bits in register CCSR */ 110 #define BS_CCM_CCSR_PDF_540M_AUTO_DIS 15 111 #define BM_CCM_CCSR_PDF_540M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_540M_AUTO_DIS) 112 #define BS_CCM_CCSR_PDF_720M_AUTO_DIS 14 113 #define BM_CCM_CCSR_PDF_720M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_720M_AUTO_DIS) 114 #define BS_CCM_CCSR_PDF_454M_AUTO_DIS 13 115 #define BM_CCM_CCSR_PDF_454M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_454M_AUTO_DIS) 116 #define BS_CCM_CCSR_PDF_508M_AUTO_DIS 12 117 #define BM_CCM_CCSR_PDF_508M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_508M_AUTO_DIS) 118 #define BS_CCM_CCSR_PDF_594M_AUTO_DIS 11 119 #define BM_CCM_CCSR_PDF_594M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_594M_AUTO_DIS) 120 #define BS_CCM_CCSR_PDF_352M_AUTO_DIS 10 121 #define BM_CCM_CCSR_PDF_352M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_352M_AUTO_DIS) 122 #define BS_CCM_CCSR_PDF_400M_AUTO_DIS 9 123 #define BM_CCM_CCSR_PDF_400M_AUTO_DIS BIT32(BS_CCM_CCSR_PDF_400M_AUTO_DIS) 124 #define BS_CCM_CCSR_STEP_SEL 8 125 #define BM_CCM_CCSR_STEP_SEL BIT32(BS_CCM_CCSR_STEP_SEL) 126 #define BS_CCM_CCSR_PLL1_SW_CLK_SEL 2 127 #define BM_CCM_CCSR_PLL1_SW_CLK_SEL BIT32(BS_CCM_CCSR_PLL1_SW_CLK_SEL) 128 #define BS_CCM_CCSR_PLL2_SW_CLK_SEL 1 129 #define BM_CCM_CCSR_PLL2_SW_CLK_SEL BIT32(BS_CCM_CCSR_PLL2_SW_CLK_SEL) 130 #define BS_CCM_CCSR_PLL3_SW_CLK_SEL 0 131 #define BM_CCM_CCSR_PLL3_SW_CLK_SEL BIT32(BS_CCM_CCSR_PLL3_SW_CLK_SEL) 132 133 /* Define the bits in register CACRR */ 134 #define BS_CCM_CACRR_ARM_PODF 0 135 #define BM_CCM_CACRR_ARM_PODF SHIFT_U32(0x7, BS_CCM_CACRR_ARM_PODF) 136 137 /* Define the bits in register CBCDR */ 138 #define BS_CCM_CBCDR_PERIPH_CLK2_PODF 27 139 #define BM_CCM_CBCDR_PERIPH_CLK2_PODF \ 140 SHIFT_U32(0x7, BS_CCM_CBCDR_PERIPH_CLK2_PODF) 141 #define BS_CCM_CBCDR_PERIPH2_CLK2_SEL 26 142 #define BM_CCM_CBCDR_PERIPH2_CLK2_SEL BIT32(BS_CCM_CBCDR_PERIPH2_CLK2_SEL) 143 #define BS_CCM_CBCDR_PERIPH_CLK_SEL 25 144 #define BM_CCM_CBCDR_PERIPH_CLK_SEL BIT32(BS_CCM_CBCDR_PERIPH_CLK_SEL) 145 #define BS_CCM_CBCDR_MMDC_CH0_PODF 19 146 #define BM_CCM_CBCDR_MMDC_CH0_PODF \ 147 SHIFT_U32(0x7, BS_CCM_CBCDR_MMDC_CH0_PODF) 148 #define BS_CCM_CBCDR_AXI_PODF 16 149 #define BM_CCM_CBCDR_AXI_PODF SHIFT_U32(0x7, BS_CCM_CBCDR_AXI_PODF) 150 #define BS_CCM_CBCDR_AHB_PODF 10 151 #define BM_CCM_CBCDR_AHB_PODF SHIFT_U32(0x7, BS_CCM_CBCDR_AHB_PODF) 152 #define BS_CCM_CBCDR_IPG_PODF 8 153 #define BM_CCM_CBCDR_IPG_PODF SHIFT_U32(0x3, BS_CCM_CBCDR_IPG_PODF) 154 #define BS_CCM_CBCDR_AXI_ALT_SEL 7 155 #define BM_CCM_CBCDR_AXI_ALT_SEL BIT32(BS_CCM_CBCDR_AXI_ALT_SEL) 156 #define BS_CCM_CBCDR_AXI_SEL 6 157 #define BM_CCM_CBCDR_AXI_SEL BIT32(BS_CCM_CBCDR_AXI_SEL) 158 #define BS_CCM_CBCDR_MMDC_CH1_PODF 3 159 #define BM_CCM_CBCDR_MMDC_CH1_PODF \ 160 SHIFT_U32(0x7, BS_CCM_CBCDR_MMDC_CH1_PODF) 161 #define BS_CCM_CBCDR_PERIPH2_CLK2_PODF 0 162 #define BM_CCM_CBCDR_PERIPH2_CLK2_PODF \ 163 SHIFT_U32(0x7, BS_CCM_CBCDR_PERIPH2_CLK2_PODF) 164 165 /* Define the bits in register CBCMR */ 166 #define BS_CCM_CBCMR_GPU3D_SHADER_PODF 29 167 #define BM_CCM_CBCMR_GPU3D_SHADER_PODF \ 168 SHIFT_U32(0x7, BS_CCM_CBCMR_GPU3D_SHADER_PODF) 169 #define BS_CCM_CBCMR_GPU3D_CORE_PODF 26 170 #define BM_CCM_CBCMR_GPU3D_CORE_PODF \ 171 SHIFT_U32(0x7, BS_CCM_CBCMR_GPU3D_CORE_PODF) 172 #define BS_CCM_CBCMR_GPU2D_CORE_PODF 23 173 #define BM_CCM_CBCMR_GPU2D_CORE_PODF \ 174 SHIFT_U32(0x7, BS_CCM_CBCMR_GPU2D_CORE_PODF) 175 #define BS_CCM_CBCMR_PRE_PERIPH2_CLK_SEL 21 176 #define BM_CCM_CBCMR_PRE_PERIPH2_CLK_SEL \ 177 SHIFT_U32(0x3, BS_CCM_CBCMR_PRE_PERIPH2_CLK_SEL) 178 #define BS_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL 20 179 #define BM_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL \ 180 BIT32(BS_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL) 181 #define BS_CCM_CBCMR_PRE_PERIPH_CLK_SEL 18 182 #define BM_CCM_CBCMR_PRE_PERIPH_CLK_SEL \ 183 SHIFT_U32(0x3, BS_CCM_CBCMR_PRE_PERIPH_CLK_SEL) 184 #define BS_CCM_CBCMR_GPU2D_CLK_SEL 16 185 #define BM_CCM_CBCMR_GPU2D_CLK_SEL \ 186 SHIFT_U32(0x3, BS_CCM_CBCMR_GPU2D_CLK_SEL) 187 #define BS_CCM_CBCMR_VPU_AXI_CLK_SEL 14 188 #define BM_CCM_CBCMR_VPU_AXI_CLK_SEL \ 189 SHIFT_U32(0x3, BS_CCM_CBCMR_VPU_AXI_CLK_SEL) 190 #define BS_CCM_CBCMR_PERIPH_CLK2_SEL 12 191 #define BM_CCM_CBCMR_PERIPH_CLK2_SEL \ 192 SHIFT_U32(0x3, BS_CCM_CBCMR_PERIPH_CLK2_SEL) 193 #define BS_CCM_CBCMR_VDOAXI_CLK_SEL 11 194 #define BM_CCM_CBCMR_VDOAXI_CLK_SEL BIT32(BS_CCM_CBCMR_VDOAXI_CLK_SEL) 195 #define BS_CCM_CBCMR_PCIE_AXI_CLK_SEL 10 196 #define BM_CCM_CBCMR_PCIE_AXI_CLK_SEL BIT32(BS_CCM_CBCMR_PCIE_AXI_CLK_SE) 197 #define BS_CCM_CBCMR_GPU3D_SHADER_CLK_SEL 8 198 #define BM_CCM_CBCMR_GPU3D_SHADER_CLK_SEL \ 199 SHIFT_U32(0x3, BS_CCM_CBCMR_GPU3D_SHADER_CLK_SEL) 200 #define BS_CCM_CBCMR_GPU3D_CORE_CLK_SEL 4 201 #define BM_CCM_CBCMR_GPU3D_CORE_CLK_SEL \ 202 SHIFT_U32(0x3, BS_CCM_CBCMR_GPU3D_CORE_CLK_SEL) 203 #define BS_CCM_CBCMR_GPU3D_AXI_CLK_SEL 1 204 #define BM_CCM_CBCMR_GPU3D_AXI_CLK_SEL \ 205 BIT32(BS_CCM_CBCMR_GPU3D_AXI_CLK_SEL) 206 #define BS_CCM_CBCMR_GPU2D_AXI_CLK_SEL 0 207 #define BM_CCM_CBCMR_GPU2D_AXI_CLK_SEL \ 208 BIT32(BS_CCM_CBCMR_GPU2D_AXI_CLK_SELx0) 209 210 /* Define the bits in register CSCMR1 */ 211 #define BS_CCM_CSCMR1_ACLK_EMI_SLOW 29 212 #define BM_CCM_CSCMR1_ACLK_EMI_SLOW \ 213 SHIFT_U32(0x3, BS_CCM_CSCMR1_ACLK_EMI_SLOW) 214 #define BS_CCM_CSCMR1_ACLK_EMI 27 215 #define BM_CCM_CSCMR1_ACLK_EMI SHIFT_U32(0x3, BS_CCM_CSCMR1_ACLK_EMI) 216 #define BS_CCM_CSCMR1_ACLK_EMI_SLOW_PODF 23 217 #define BM_CCM_CSCMR1_ACLK_EMI_SLOW_PODF \ 218 SHIFT_U32(0x7, BS_CCM_CSCMR1_ACLK_EMI_SLOW_PODF) 219 #define BS_CCM_CSCMR1_ACLK_EMI_PODF 20 220 #define BM_CCM_CSCMR1_ACLK_EMI_PODF \ 221 SHIFT_U32(0x7, BS_CCM_CSCMR1_ACLK_EMI_PODF) 222 #define BS_CCM_CSCMR1_USDHC4_CLK_SEL 19 223 #define BM_CCM_CSCMR1_USDHC4_CLK_SEL \ 224 BIT32(BS_CCM_CSCMR1_USDHC4_CLK_SEL) 225 #define BS_CCM_CSCMR1_USDHC3_CLK_SEL 18 226 #define BM_CCM_CSCMR1_USDHC3_CLK_SEL \ 227 BIT32(BS_CCM_CSCMR1_USDHC3_CLK_SEL) 228 #define BS_CCM_CSCMR1_USDHC2_CLK_SEL 17 229 #define BM_CCM_CSCMR1_USDHC2_CLK_SEL \ 230 BIT32(BS_CCM_CSCMR1_USDHC2_CLK_SEL) 231 #define BS_CCM_CSCMR1_USDHC1_CLK_SEL 16 232 #define BM_CCM_CSCMR1_USDHC1_CLK_SEL \ 233 BIT32(BS_CCM_CSCMR1_USDHC1_CLK_SEL) 234 #define BS_CCM_CSCMR1_SSI3_CLK_SEL 14 235 #define BM_CCM_CSCMR1_SSI3_CLK_SEL \ 236 SHIFT_U32(0x3, BS_CCM_CSCMR1_SSI3_CLK_SEL) 237 #define BS_CCM_CSCMR1_SSI2_CLK_SEL 12 238 #define BM_CCM_CSCMR1_SSI2_CLK_SEL \ 239 SHIFT_U32(0x3, BS_CCM_CSCMR1_SSI2_CLK_SEL) 240 #define BS_CCM_CSCMR1_SSI1_CLK_SEL 10 241 #define BM_CCM_CSCMR1_SSI1_CLK_SEL \ 242 SHIFT_U32(0x3, BS_CCM_CSCMR1_SSI1_CLK_SEL) 243 #define BS_CCM_CSCMR1_PERCLK_PODF 0 244 #define BM_CCM_CSCMR1_PERCLK_PODF \ 245 SHIFT_U32(0x3F, BS_CCM_CSCMR1_PERCLK_PODF) 246 247 /* Define the bits in register CSCMR2 */ 248 #define BS_CCM_CSCMR2_ESAI_PRE_SEL 19 249 #define BM_CCM_CSCMR2_ESAI_PRE_SEL \ 250 SHIFT_U32(0x3, BS_CCM_CSCMR2_ESAI_PRE_SEL) 251 #define BS_CCM_CSCMR2_LDB_DI1_IPU_DIV 11 252 #define BM_CCM_CSCMR2_LDB_DI1_IPU_DIV BIT32(BS_CCM_CSCMR2_LDB_DI1_IPU_DIV) 253 #define BS_CCM_CSCMR2_LDB_DI0_IPU_DIV 10 254 #define BM_CCM_CSCMR2_LDB_DI0_IPU_DIV BIT32(BS_CCM_CSCMR2_LDB_DI1_IPU_DIV) 255 #define BS_CCM_CSCMR2_CAN_CLK_SEL 2 256 #define BM_CCM_CSCMR2_CAN_CLK_SEL \ 257 SHIFT_U32(0x3F, BS_CCM_CSCMR2_CAN_CLK_SEL) 258 259 /* Define the bits in register CSCDR1 */ 260 #define BS_CCM_CSCDR1_VPU_AXI_PODF 25 261 #define BM_CCM_CSCDR1_VPU_AXI_PODF \ 262 SHIFT_U32(0x7, BS_CCM_CSCDR1_VPU_AXI_PODF) 263 #define BS_CCM_CSCDR1_USDHC4_PODF 22 264 #define BM_CCM_CSCDR1_USDHC4_PODF \ 265 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC4_PODF) 266 #define BS_CCM_CSCDR1_USDHC3_PODF 19 267 #define BM_CCM_CSCDR1_USDHC3_PODF \ 268 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC3_PODF) 269 #define BS_CCM_CSCDR1_USDHC2_PODF 16 270 #define BM_CCM_CSCDR1_USDHC2_PODF \ 271 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC2_PODF) 272 #define BS_CCM_CSCDR1_USDHC1_PODF 11 273 #define BM_CCM_CSCDR1_USDHC1_PODF \ 274 SHIFT_U32(0x7, BS_CCM_CSCDR1_USDHC1_PODF) 275 #define BS_CCM_CSCDR1_USBOH3_CLK_PRED 8 276 #define BM_CCM_CSCDR1_USBOH3_CLK_PRED \ 277 SHIFT_U32(0x7, BS_CCM_CSCDR1_USBOH3_CLK_PRED) 278 #define BS_CCM_CSCDR1_USBOH3_CLK_PODF 6 279 #define BM_CCM_CSCDR1_USBOH3_CLK_PODF \ 280 SHIFT_U32(0x3, BS_CCM_CSCDR1_USBOH3_CLK_PODF) 281 #ifdef CONFIG_MX6SL 282 #define BS_CCM_CSCDR1_UART_CLK_SEL 6 283 #define BM_CCM_CSCDR1_UART_CLK_SEL BIT32(BS_CCM_CSCDR1_UART_CLK_SEL) 284 #define BS_CCM_CSCDR1_UART_CLK_PODF 0 285 #define BM_CCM_CSCDR1_UART_CLK_PODF SHIFT_U32(0x1F, BS_CCM_CSCDR1_UA) 286 #else 287 #define BS_CCM_CSCDR1_UART_CLK_PODF 0 288 #define BM_CCM_CSCDR1_UART_CLK_PODF \ 289 SHIFT_U32(0x3F, BS_CCM_CSCDR1_UART_CLK_PODF) 290 #endif 291 292 /* Define the bits in register CS1CDR */ 293 #define BS_CCM_CS1CDR_ESAI_CLK_PODF 25 294 #define BM_CCM_CS1CDR_ESAI_CLK_PODF \ 295 SHIFT_U32(0x3F, BS_CCM_CS1CDR_ESAI_CLK_PODF) 296 #define BS_CCM_CS1CDR_SSI3_CLK_PODF 16 297 #define BM_CCM_CS1CDR_SSI3_CLK_PODF SHIFT_U32(0x3F, BS_CCM_CS1CDR_SSI3) 298 #define BS_CCM_CS1CDR_ESAI_CLK_PRED 9 299 #define BM_CCM_CS1CDR_ESAI_CLK_PRED \ 300 SHIFT_U32(0x3, BS_CCM_CS1CDR_ESAI_CLK_PRED) 301 #define BS_CCM_CS1CDR_SSI1_CLK_PRED 6 302 #define BM_CCM_CS1CDR_SSI1_CLK_PRED \ 303 SHIFT_U32(0x7, BS_CCM_CS1CDR_SSI1_CLK_PRED) 304 #define BS_CCM_CS1CDR_SSI1_CLK_PODF 0 305 #define BM_CCM_CS1CDR_SSI1_CLK_PODF \ 306 SHIFT_U32(0x3F, BS_CCM_CS1CDR_SSI1_CLK_PODF) 307 308 /* Define the bits in register CS2CDR */ 309 #define BS_CCM_CS2CDR_ENFC_CLK_PODF 21 310 #define BM_CCM_CS2CDR_ENFC_CLK_PODF \ 311 SHIFT_U32(0x3F, BS_CCM_CS2CDR_ENFC_CLK_PODF) 312 #define CCM_CS2CDR_ENFC_CLK_PODF(v) \ 313 (SHIFT_U32(v, BS_CCM_CS2CDR_ENFC_CLK_PODF) & \ 314 BM_CCM_CS2CDR_ENFC_CLK_PODF) 315 #define BS_CCM_CS2CDR_ENFC_CLK_PRED 18 316 #define BM_CCM_CS2CDR_ENFC_CLK_PRED \ 317 SHIFT_U32(0x7, BS_CCM_CS2CDR_ENFC_CLK_PRED) 318 #define CCM_CS2CDR_ENFC_CLK_PRED(v) \ 319 (SHIFT_U32(v, BS_CCM_CS2CDR_ENFC_CLK_PRED) & \ 320 BM_CCM_CS2CDR_ENFC_CLK_PRED) 321 #define BS_CCM_CS2CDR_ENFC_CLK_SEL 16 322 #define BM_CCM_CS2CDR_ENFC_CLK_SEL \ 323 SHIFT_U32(0x3, BS_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) 324 #define CCM_CS2CDR_ENFC_CLK_SEL(v) \ 325 (SHIFT_U32(v, BS_CCM_CS2CDR_ENFC_CLK_SEL) & \ 326 BM_CCM_CS2CDR_ENFC_CLK_SEL) 327 #define BS_CCM_CS2CDR_LDB_DI1_CLK_SEL 12 328 #define BM_CCM_CS2CDR_LDB_DI1_CLK_SEL \ 329 SHIFT_U32(0x7, BS_CCM_CS2CDR_LDB_DI1_CLK_SEL) 330 #define BS_CCM_CS2CDR_LDB_DI0_CLK_SEL 9 331 #define BM_CCM_CS2CDR_LDB_DI0_CLK_SEL \ 332 SHIFT_U32(0x7, BS_CCM_CS2CDR_LDB_DI0_CLK_SEL) 333 #define BS_CCM_CS2CDR_SSI2_CLK_PRED 6 334 #define BM_CCM_CS2CDR_SSI2_CLK_PRED \ 335 SHIFT_U32(0x7, BS_CCM_CS2CDR_SSI2_CLK_PRED) 336 #define BS_CCM_CS2CDR_SSI2_CLK_PODF 0 337 #define BM_CCM_CS2CDR_SSI2_CLK_PODF \ 338 SHIFT_U32(0x3F, BS_CCM_CS2CDR_SSI2_CLK_PODF) 339 340 /* Define the bits in register CDCDR */ 341 #define BS_CCM_CDCDR_HSI_TX_PODF 29 342 #define BM_CCM_CDCDR_HSI_TX_PODF \ 343 SHIFT_U32(0x7, BS_CCM_CDCDR_HSI_TX_PODF) 344 #define BS_CCM_CDCDR_SPDIF0_CLK_PRED 25 345 #define BM_CCM_CDCDR_SPDIF0_CLK_PRED \ 346 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF0_CLK_PRED) 347 #define BS_CCM_CDCDR_HSI_TX_CLK_SEL 28 348 #define BM_CCM_CDCDR_HSI_TX_CLK_SEL \ 349 BIT32(BS_CCM_CDCDR_HSI_TX_CLK_SEL) 350 #define BS_CCM_CDCDR_SPDIF0_CLK_PODF 19 351 #define BM_CCM_CDCDR_SPDIF0_CLK_PODF \ 352 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF0_CLK_PODF) 353 #define BS_CCM_CDCDR_SPDIF0_CLK_SEL 20 354 #define BM_CCM_CDCDR_SPDIF0_CLK_SEL \ 355 SHIFT_U32(0x3, BS_CCM_CDCDR_SPDIF0_CLK_SEL) 356 #define BS_CCM_CDCDR_SPDIF1_CLK_PRED 12 357 #define BM_CCM_CDCDR_SPDIF1_CLK_PRED \ 358 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF1_CLK_PRED) 359 #define BS_CCM_CDCDR_SPDIF1_CLK_PODF 9 360 #define BM_CCM_CDCDR_SPDIF1_CLK_PODF \ 361 SHIFT_U32(0x7, BS_CCM_CDCDR_SPDIF1_CLK_PODF) 362 #define BS_CCM_CDCDR_SPDIF1_CLK_SEL 7 363 #define BM_CCM_CDCDR_SPDIF1_CLK_SEL \ 364 SHIFT_U32(0x3, BS_CCM_CDCDR_SPDIF1_CLK_SEL) 365 366 /* Define the bits in register CHSCCDR */ 367 #define BS_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL 15 368 #define BM_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL \ 369 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL) 370 #define BS_CCM_CHSCCDR_IPU1_DI1_PODF 12 371 #define BM_CCM_CHSCCDR_IPU1_DI1_PODF \ 372 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI1_PODF) 373 #define BS_CCM_CHSCCDR_IPU1_DI1_CLK_SEL 9 374 #define BM_CCM_CHSCCDR_IPU1_DI1_CLK_SEL \ 375 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI1_CLK_SEL) 376 #define BS_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL 6 377 #define BM_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL \ 378 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL) 379 #define BS_CCM_CHSCCDR_IPU1_DI0_PODF 3 380 #define BM_CCM_CHSCCDR_IPU1_DI0_PODF \ 381 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI0_PODF) 382 #define BS_CCM_CHSCCDR_IPU1_DI0_CLK_SEL 0 383 #define BM_CCM_CHSCCDR_IPU1_DI0_CLK_SEL \ 384 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU1_DI0_CLK_SEL) 385 386 #define CHSCCDR_CLK_SEL_LDB_DI0 3 387 #define CHSCCDR_PODF_DIVIDE_BY_3 2 388 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 389 390 /* Define the bits in register CSCDR2 */ 391 #define BS_CCM_CSCDR2_ECSPI_CLK_PODF 19 392 #define BM_CCM_CSCDR2_ECSPI_CLK_PODF \ 393 SHIFT_U32(0x3F, BS_CCM_CSCDR2_ECSPI_CLK_PODF) 394 #define BS_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL 15 395 #define BM_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL \ 396 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL) 397 #define BS_CCM_CHSCCDR_IPU2_DI1_PODF 12 398 #define BM_CCM_CHSCCDR_IPU2_DI1_PODF \ 399 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI1_PODF) 400 #define BS_CCM_CHSCCDR_IPU2_DI1_CLK_SEL 9 401 #define BM_CCM_CHSCCDR_IPU2_DI1_CLK_SEL \ 402 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI1_CLK_SEL) 403 #define BS_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL 6 404 #define BM_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL \ 405 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL) 406 #define BS_CCM_CHSCCDR_IPU2_DI0_PODF 3 407 #define BM_CCM_CHSCCDR_IPU2_DI0_PODF \ 408 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI0_PODF) 409 #define BS_CCM_CHSCCDR_IPU2_DI0_CLK_SEL 0 410 #define BM_CCM_CHSCCDR_IPU2_DI0_CLK_SEL \ 411 SHIFT_U32(0x7, BS_CCM_CHSCCDR_IPU2_DI0_CLK_SEL) 412 413 /* Define the bits in register CSCDR3 */ 414 #define BS_CCM_CSCDR3_IPU2_HSP_PODF 16 415 #define BM_CCM_CSCDR3_IPU2_HSP_PODF \ 416 SHIFT_U32(0x7, BS_CCM_CSCDR3_IPU2_HSP_PODF) 417 #define BS_CCM_CSCDR3_IPU2_HSP_CLK_SEL 14 418 #define BM_CCM_CSCDR3_IPU2_HSP_CLK_SEL \ 419 SHIFT_U32(0x3, BS_CCM_CSCDR3_IPU2_HSP_CLK_SEL) 420 #define BS_CCM_CSCDR3_IPU1_HSP_PODF 11 421 #define BM_CCM_CSCDR3_IPU1_HSP_PODF \ 422 SHIFT_U32(0x7, BS_CCM_CSCDR3_IPU1_HSP_PODF) 423 #define BS_CCM_CSCDR3_IPU1_HSP_CLK_SEL 9 424 #define BM_CCM_CSCDR3_IPU1_HSP_CLK_SEL \ 425 SHIFT_U32(0x3, BS_CCM_CSCDR3_IPU1_HSP_CLK_SEL) 426 427 /* Define the bits in register CDHIPR */ 428 #define BS_CCM_CDHIPR_ARM_PODF_BUSY 16 429 #define BM_CCM_CDHIPR_ARM_PODF_BUSY \ 430 BIT32(BS_CCM_CDHIPR_ARM_PODF_BUSY) 431 #define BS_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY 5 432 #define BM_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY \ 433 BIT32(BS_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) 434 #define BS_CCM_CDHIPR_MMDC_CH0_PODF_BUSY 4 435 #define BM_CCM_CDHIPR_MMDC_CH0_PODF_BUSY \ 436 BIT32(BS_CCM_CDHIPR_MMDC_CH0_PODF_BUSY) 437 #define BS_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY 3 438 #define BM_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY \ 439 BIT32(BS_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) 440 #define BS_CCM_CDHIPR_MMDC_CH1_PODF_BUSY 2 441 #define BM_CCM_CDHIPR_MMDC_CH1_PODF_BUSY \ 442 BIT32(BS_CCM_CDHIPR_MMDC_CH1_PODF_BUSY) 443 #define BS_CCM_CDHIPR_AHB_PODF_BUSY 1 444 #define BM_CCM_CDHIPR_AHB_PODF_BUSY \ 445 BIT32(BS_CCM_CDHIPR_AHB_PODF_BUSY) 446 #define BS_CCM_CDHIPR_AXI_PODF_BUSY 0 447 #define BM_CCM_CDHIPR_AXI_PODF_BUSY \ 448 BIT32(BS_CCM_CDHIPR_AXI_PODF_BUSY) 449 450 /* Define the bits in register CLPCR */ 451 #define BS_CCM_CLPCR_MASK_L2CC_IDLE 27 452 #define BM_CCM_CLPCR_MASK_L2CC_IDLE \ 453 BIT32(BS_CCM_CLPCR_MASK_L2CC_IDLE) 454 #define BS_CCM_CLPCR_MASK_SCU_IDLE 26 455 #define BM_CCM_CLPCR_MASK_SCU_IDLE \ 456 BIT32(BS_CCM_CLPCR_MASK_SCU_IDLE) 457 #define BS_CCM_CLPCR_MASK_CORE3_WFI 25 458 #define BM_CCM_CLPCR_MASK_CORE3_WFI \ 459 BIT32(BS_CCM_CLPCR_MASK_CORE3_WFI) 460 #define BS_CCM_CLPCR_MASK_CORE2_WFI 24 461 #define BM_CCM_CLPCR_MASK_CORE2_WFI \ 462 BIT32(BS_CCM_CLPCR_MASK_CORE2_WFI) 463 #define BS_CCM_CLPCR_MASK_CORE1_WFI 23 464 #define BM_CCM_CLPCR_MASK_CORE1_WFI \ 465 BIT32(BS_CCM_CLPCR_MASK_CORE1_WFI) 466 #define BS_CCM_CLPCR_MASK_CORE0_WFI 22 467 #define BM_CCM_CLPCR_MASK_CORE0_WFI \ 468 BIT32(BS_CCM_CLPCR_MASK_CORE0_WFI) 469 #define BS_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS 21 470 #define BM_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS \ 471 BIT32(BS_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS) 472 #define BS_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS 19 473 #define BM_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS \ 474 BIT32(BS_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS) 475 #define BS_CCM_CLPCR_WB_CORE_AT_LPM 17 476 #define BM_CCM_CLPCR_WB_CORE_AT_LPM \ 477 BIT32(BS_CCM_CLPCR_WB_CORE_AT_LPM) 478 #define BS_CCM_CLPCR_WB_PER_AT_LPM 16 479 #define BM_CCM_CLPCR_WB_PER_AT_LPM \ 480 BIT32(BS_CCM_CLPCR_WB_PER_AT_LPM) 481 #define BS_CCM_CLPCR_COSC_PWRDOWN 11 482 #define BM_CCM_CLPCR_COSC_PWRDOWN \ 483 BIT32(BS_CCM_CLPCR_COSC_PWRDOWN) 484 #define BS_CCM_CLPCR_STBY_COUNT 9 485 #define BM_CCM_CLPCR_STBY_COUNT \ 486 SHIFT_U32(0x3, BS_CCM_CLPCR_STBY_COUNT) 487 #define BS_CCM_CLPCR_VSTBY 8 488 #define BM_CCM_CLPCR_VSTBY \ 489 BIT32(BS_CCM_CLPCR_VSTBY) 490 #define BS_CCM_CLPCR_DIS_REF_OSC 7 491 #define BM_CCM_CLPCR_DIS_REF_OSC \ 492 BIT32(BS_CCM_CLPCR_DIS_REF_OSC) 493 #define BS_CCM_CLPCR_SBYOS 6 494 #define BM_CCM_CLPCR_SBYOS \ 495 BIT32(BS_CCM_CLPCR_SBYOS) 496 #define BS_CCM_CLPCR_ARM_CLK_DIS_ON_LPM 5 497 #define BM_CCM_CLPCR_ARM_CLK_DIS_ON_LPM \ 498 BIT32(BS_CCM_CLPCR_ARM_CLK_DIS_ON_LPM) 499 #define BS_CCM_CLPCR_LPSR_CLK_SEL 3 500 #define BM_CCM_CLPCR_LPSR_CLK_SEL \ 501 SHIFT_U32(0x3, BS_CCM_CLPCR_LPSR_CLK_SEL) 502 #define BS_CCM_CLPCR_BYPASS_PMIC_VFUNC_RDY 2 503 #define BM_CCM_CLPCR_BYPASS_PMIC_VFUNC_RDY \ 504 BIT32(BS_CCM_CLPCR_BYPASS_PMIC_VFUNC_RDY) 505 #define BS_CCM_CLPCR_LPM 0 506 #define BM_CCM_CLPCR_LPM \ 507 SHIFT_U32(0x3, BS_CCM_CLPCR_LPM) 508 509 /* Define the bits in register CISR */ 510 #define BS_CCM_CISR_ARM_PODF_LOADED 26 511 #define BM_CCM_CISR_ARM_PODF_LOADED \ 512 BIT32(BS_CCM_CISR_ARM_PODF_LOADED) 513 #define BS_CCM_CISR_MMDC_CH0_PODF_LOADED 23 514 #define BM_CCM_CISR_MMDC_CH0_PODF_LOADED \ 515 BIT32(BS_CCM_CISR_MMDC_CH0_PODF_LOADED) 516 #define BS_CCM_CISR_PERIPH_CLK_SEL_LOADED 22 517 #define BM_CCM_CISR_PERIPH_CLK_SEL_LOADED \ 518 BIT32(BS_CCM_CISR_PERIPH_CLK_SEL_LOADED) 519 #define BS_CCM_CISR_MMDC_CH1_PODF_LOADED 21 520 #define BM_CCM_CISR_MMDC_CH1_PODF_LOADED \ 521 BIT32(BS_CCM_CISR_MMDC_CH1_PODF_LOADED) 522 #define BS_CCM_CISR_AHB_PODF_LOADED 20 523 #define BM_CCM_CISR_AHB_PODF_LOADED \ 524 BIT32(BS_CCM_CISR_AHB_PODF_LOADED) 525 #define BS_CCM_CISR_PERIPH2_CLK_SEL_LOADED 19 526 #define BM_CCM_CISR_PERIPH2_CLK_SEL_LOADED \ 527 BIT32(BS_CCM_CISR_PERIPH2_CLK_SEL_LOADED) 528 #define BS_CCM_CISR_AXI_PODF_LOADED 17 529 #define BM_CCM_CISR_AXI_PODF_LOADED \ 530 BIT32(BS_CCM_CISR_AXI_PODF_LOADED) 531 #define BS_CCM_CISR_COSC_READY 6 532 #define BM_CCM_CISR_COSC_READY \ 533 BIT32(BS_CCM_CISR_COSC_READY) 534 #define BS_CCM_CISR_LRF_PLL 0 535 #define BM_CCM_CISR_LRF_PLL \ 536 BIT32(BS_CCM_CISR_LRF_PLL) 537 538 /* Define the bits in register CIMR */ 539 #define BS_CCM_CIMR_MASK_ARM_PODF_LOADED 26 540 #define BM_CCM_CIMR_MASK_ARM_PODF_LOADED \ 541 BIT32(BS_CCM_CIMR_MASK_ARM_PODF_LOADED) 542 #define BS_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED 23 543 #define BM_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED \ 544 BIT32(BS_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED) 545 #define BS_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED 22 546 #define BM_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED \ 547 BIT32(BS_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED) 548 #define BS_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED 21 549 #define BM_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED \ 550 BIT32(BS_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED) 551 #define BS_CCM_CIMR_MASK_AHB_PODF_LOADED 20 552 #define BM_CCM_CIMR_MASK_AHB_PODF_LOADED \ 553 BIT32(BS_CCM_CIMR_MASK_AHB_PODF_LOADED) 554 #define BS_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED 19 555 #define BM_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED \ 556 BIT32(BS_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED) 557 #define BS_CCM_CIMR_MASK_AXI_PODF_LOADED 17 558 #define BM_CCM_CIMR_MASK_AXI_PODF_LOADED \ 559 BIT32(BS_CCM_CIMR_MASK_AXI_PODF_LOADED) 560 #define BS_CCM_CIMR_MASK_COSC_READY 6 561 #define BM_CCM_CIMR_MASK_COSC_READY \ 562 BIT32(BS_CCM_CIMR_MASK_COSC_READY) 563 #define BS_CCM_CIMR_MASK_LRF_PLL 0 564 #define BM_CCM_CIMR_MASK_LRF_PLL \ 565 BIT32(BS_CCM_CIMR_MASK_LRF_PLL) 566 567 /* Define the bits in register CCOSR */ 568 #define BS_CCM_CCOSR_CKO2_EN 24 569 #define BM_CCM_CCOSR_CKO2_EN \ 570 BIT32(BS_CCM_CCOSR_CKO2_EN) 571 #define BS_CCM_CCOSR_CKO2_DIV 21 572 #define BM_CCM_CCOSR_CKO2_DIV \ 573 SHIFT_U32(0x7, BS_CCM_CCOSR_CKO2_DIV) 574 #define BS_CCM_CCOSR_CKO2_SEL 16 575 #define BM_CCM_CCOSR_CKO2_SEL \ 576 SHIFT_U32(0x1F, BS_CCM_CCOSR_CKO2_SEL) 577 #define BS_CCM_CCOSR_CLK_OUT_SEL 8 578 #define BM_CCM_CCOSR_CLK_OUT_SEL_CKO2 \ 579 BIT32(BS_CCM_CCOSR_CLK_OUT_SEL) 580 #define BS_CCM_CCOSR_CKOL_EN 7 581 #define BM_CCM_CCOSR_CKOL_EN \ 582 BIT32(BS_CCM_CCOSR_CKOL_EN) 583 #define BS_CCM_CCOSR_CKOL_DIV 4 584 #define BM_CCM_CCOSR_CKOL_DIV \ 585 SHIFT_U32(0x7, BS_CCM_CCOSR_CKOL_DIV) 586 #define BS_CCM_CCOSR_CKOL_SEL 0 587 #define BM_CCM_CCOSR_CKOL_SEL \ 588 SHIFT_U32(0xF, BS_CCM_CCOSR_CKOL_SEL) 589 590 /* Define the bits in registers CGPR */ 591 #define BS_CCM_CGPR_INT_MEM_CLK_LPM 17 592 #define BM_CCM_CGPR_INT_MEM_CLK_LPM \ 593 BIT32(BS_CCM_CGPR_INT_MEM_CLK_LPM) 594 #define BS_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE 4 595 #define BM_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE \ 596 BIT32(BS_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE) 597 #define BS_CCM_CGPR_MMDC_EXT_CLK_DIS 2 598 #define BM_CCM_CGPR_MMDC_EXT_CLK_DIS \ 599 BIT32(BS_CCM_CGPR_MMDC_EXT_CLK_DIS) 600 #define BS_CCM_CGPR_PMIC_DELAY_SCALER 0 601 #define BM_CCM_CGPR_PMIC_DELAY_SCALER \ 602 BIT32(BS_CCM_CGPR_PMIC_DELAY_SCALER) 603 604 /* Define the bits in registers CCGRx */ 605 #define BS_CCM_CCGR0_AIPS_TZ1 0 606 #define BM_CCM_CCGR0_AIPS_TZ1 \ 607 SHIFT_U32(3, BS_CCM_CCGR0_AIPS_TZ1) 608 #define BS_CCM_CCGR0_AIPS_TZ2 2 609 #define BM_CCM_CCGR0_AIPS_TZ2 \ 610 SHIFT_U32(3, BS_CCM_CCGR0_AIPS_TZ2) 611 #define BS_CCM_CCGR0_APBHDMA 4 612 #define BM_CCM_CCGR0_APBHDMA \ 613 SHIFT_U32(3, BS_CCM_CCGR0_APBHDMA) 614 #define BS_CCM_CCGR0_ASRC 6 615 #define BM_CCM_CCGR0_ASRC \ 616 SHIFT_U32(3, BS_CCM_CCGR0_ASRC) 617 #define BS_CCM_CCGR0_CAAM_SECURE_MEM 8 618 #define BM_CCM_CCGR0_CAAM_SECURE_MEM \ 619 SHIFT_U32(3, BS_CCM_CCGR0_CAAM_SECURE_MEM) 620 #define BS_CCM_CCGR0_CAAM_WRAPPER_ACLK 10 621 #define BM_CCM_CCGR0_CAAM_WRAPPER_ACLK \ 622 SHIFT_U32(3, BS_CCM_CCGR0_CAAM_WRAPPER_ACLK) 623 #define BS_CCM_CCGR0_CAAM_WRAPPER_IPG 12 624 #define BM_CCM_CCGR0_CAAM_WRAPPER_IPG \ 625 SHIFT_U32(3, BS_CCM_CCGR0_CAAM_WRAPPER_IPG) 626 #define BS_CCM_CCGR0_CAN1 14 627 #define BM_CCM_CCGR0_CAN1 SHIFT_U32(3, BS_CCM_CCGR0_CAN1) 628 #define BS_CCM_CCGR0_CAN1_SERIAL 16 629 #define BM_CCM_CCGR0_CAN1_SERIAL \ 630 SHIFT_U32(3, BS_CCM_CCGR0_CAN1_SERIAL) 631 #define BS_CCM_CCGR0_CAN2 18 632 #define BM_CCM_CCGR0_CAN2 SHIFT_U32(3, BS_CCM_CCGR0_CAN2) 633 #define BS_CCM_CCGR0_CAN2_SERIAL 20 634 #define BM_CCM_CCGR0_CAN2_SERIAL \ 635 SHIFT_U32(3, BS_CCM_CCGR0_CAN2_SERIAL) 636 #define BS_CCM_CCGR0_CHEETAH_DBG_CLK 22 637 #define BM_CCM_CCGR0_CHEETAH_DBG_CLK \ 638 SHIFT_U32(3, BS_CCM_CCGR0_CHEETAH_DBG_CLK) 639 #define BS_CCM_CCGR0_DCIC1 24 640 #define BM_CCM_CCGR0_DCIC1 SHIFT_U32(3, BS_CCM_CCGR0_DCIC1) 641 #define BS_CCM_CCGR0_DCIC2 26 642 #define BM_CCM_CCGR0_DCIC2 SHIFT_U32(3, BS_CCM_CCGR0_DCIC2) 643 #define BS_CCM_CCGR0_DTCP 28 644 #define BM_CCM_CCGR0_DTCP SHIFT_U32(3, BS_CCM_CCGR0_DTCP) 645 646 #define BS_CCM_CCGR1_ECSPI1S 0 647 #define BM_CCM_CCGR1_ECSPI1S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI1S) 648 #define BS_CCM_CCGR1_ECSPI2S 2 649 #define BM_CCM_CCGR1_ECSPI2S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI2S) 650 #define BS_CCM_CCGR1_ECSPI3S 4 651 #define BM_CCM_CCGR1_ECSPI3S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI3S) 652 #define BS_CCM_CCGR1_ECSPI4S 6 653 #define BM_CCM_CCGR1_ECSPI4S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI4S) 654 #define BS_CCM_CCGR1_ECSPI5S 8 655 #define BM_CCM_CCGR1_ECSPI5S SHIFT_U32(3, BS_CCM_CCGR1_ECSPI5S) 656 #define BS_CCM_CCGR1_ENET_CLK_ENABLE 10 657 #define BM_CCM_CCGR1_ENET_CLK_ENABLE \ 658 (3 << BS_CCM_CCGR1_ENET_CLK_ENABLE) 659 #define BS_CCM_CCGR1_EPIT1S 12 660 #define BM_CCM_CCGR1_EPIT1S SHIFT_U32(3, BS_CCM_CCGR1_EPIT1S) 661 #define BS_CCM_CCGR1_EPIT2S 14 662 #define BM_CCM_CCGR1_EPIT2S SHIFT_U32(3, BS_CCM_CCGR1_EPIT2S) 663 #define BS_CCM_CCGR1_ESAIS 16 664 #define BM_CCM_CCGR1_ESAIS SHIFT_U32(3, BS_CCM_CCGR1_ESAIS) 665 #define BS_CCM_CCGR1_GPT_BUS 20 666 #define BM_CCM_CCGR1_GPT_BUS SHIFT_U32(3, BS_CCM_CCGR1_GPT_BUS) 667 #define BS_CCM_CCGR1_GPT_SERIAL 22 668 #define BM_CCM_CCGR1_GPT_SERIAL SHIFT_U32(3, BS_CCM_CCGR1_GPT_SERIAL) 669 #define BS_CCM_CCGR1_GPU2D 24 670 #define BM_CCM_CCGR1_GPU2D SHIFT_U32(3, BS_CCM_CCGR1_GPU2D) 671 #define BS_CCM_CCGR1_GPU3D 26 672 #define BM_CCM_CCGR1_GPU3D SHIFT_U32(3, BS_CCM_CCGR1_GPU3D) 673 674 #define BS_CCM_CCGR2_HDMI_TX_IAHBCLK 0 675 #define BM_CCM_CCGR2_HDMI_TX_IAHBCLK \ 676 SHIFT_U32(3, BS_CCM_CCGR2_HDMI_TX_IAHBCLK) 677 #define BS_CCM_CCGR2_HDMI_TX_ISFRCLK 4 678 #define BM_CCM_CCGR2_HDMI_TX_ISFRCLK \ 679 SHIFT_U32(3, BS_CCM_CCGR2_HDMI_TX_ISFRCLK) 680 #define BS_CCM_CCGR2_I2C1_SERIAL 6 681 #define BM_CCM_CCGR2_I2C1_SERIAL SHIFT_U32(3, BS_CCM_CCGR2_I2C1_SERIAL) 682 #define BS_CCM_CCGR2_I2C2_SERIAL 8 683 #define BM_CCM_CCGR2_I2C2_SERIAL SHIFT_U32(3, BS_CCM_CCGR2_I2C2_SERIAL) 684 #define BS_CCM_CCGR2_I2C3_SERIAL 10 685 #define BM_CCM_CCGR2_I2C3_SERIAL SHIFT_U32(3, BS_CCM_CCGR2_I2C3_SERIAL) 686 #define BS_CCM_CCGR2_OCOTP_CTRL 12 687 #define BM_CCM_CCGR2_OCOTP_CTRL SHIFT_U32(3, BS_CCM_CCGR2_OCOTP_CTRL) 688 #define BS_CCM_CCGR2_IOMUX_IPT_CLK_IO 14 689 #define BM_CCM_CCGR2_IOMUX_IPT_CLK_IO \ 690 SHIFT_U32(3, BS_CCM_CCGR2_IOMUX_IPT_CLK_IO) 691 #define BS_CCM_CCGR2_IPMUX1 16 692 #define BM_CCM_CCGR2_IPMUX1 SHIFT_U32(3, BS_CCM_CCGR2_IPMUX1) 693 #define BS_CCM_CCGR2_IPMUX2 18 694 #define BM_CCM_CCGR2_IPMUX2 SHIFT_U32(3, BS_CCM_CCGR2_IPMUX2) 695 #define BS_CCM_CCGR2_IPMUX3 20 696 #define BM_CCM_CCGR2_IPMUX3 SHIFT_U32(3, BS_CCM_CCGR2_IPMUX3) 697 #define BS_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS 22 698 #define BM_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS \ 699 SHIFT_U32(3, BS_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS) 700 #define BS_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG 24 701 #define BM_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG \ 702 SHIFT_U32(3, BS_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG) 703 #define BS_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK 26 704 #define BM_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK \ 705 SHIFT_U32(3, BS_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK) 706 707 #define BS_CCM_CCGR3_IPU1_IPU 0 708 #define BM_CCM_CCGR3_IPU1_IPU SHIFT_U32(3, BS_CCM_CCGR3_IPU1_IPU) 709 #define BS_CCM_CCGR3_IPU1_IPU_DI0 2 710 #define BM_CCM_CCGR3_IPU1_IPU_DI0 SHIFT_U32(3, BS_CCM_CCGR3_IPU1_IPU_DI0) 711 #define BS_CCM_CCGR3_IPU1_IPU_DI1 4 712 #define BM_CCM_CCGR3_IPU1_IPU_DI1 SHIFT_U32(3, BS_CCM_CCGR3_IPU1_IPU_DI1) 713 #define BS_CCM_CCGR3_IPU2_IPU 6 714 #define BM_CCM_CCGR3_IPU2_IPU SHIFT_U32(3, BS_CCM_CCGR3_IPU2_IPU) 715 #define BS_CCM_CCGR3_IPU2_IPU_DI0 8 716 #define BM_CCM_CCGR3_IPU2_IPU_DI0 SHIFT_U32(3, BS_CCM_CCGR3_IPU2_IPU_DI0) 717 #define BS_CCM_CCGR3_IPU2_IPU_DI1 10 718 #define BM_CCM_CCGR3_IPU2_IPU_DI1 SHIFT_U32(3, BS_CCM_CCGR3_IPU2_IPU_DI1) 719 #define BS_CCM_CCGR3_LDB_DI0 12 720 #define BM_CCM_CCGR3_LDB_DI0 SHIFT_U32(3, BS_CCM_CCGR3_LDB_DI0) 721 #define BS_CCM_CCGR3_LDB_DI1 14 722 #define BM_CCM_CCGR3_LDB_DI1 SHIFT_U32(3, BS_CCM_CCGR3_LDB_DI1) 723 #define BS_CCM_CCGR3_MIPI_CORE_CFG 16 724 #define BM_CCM_CCGR3_MIPI_CORE_CFG \ 725 SHIFT_U32(3, BS_CCM_CCGR3_MIPI_CORE_CFG) 726 #define BS_CCM_CCGR3_MLB 18 727 #define BM_CCM_CCGR3_MLB SHIFT_U32(3, BS_CCM_CCGR3_MLB) 728 #define BS_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0 20 729 #define BM_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0 \ 730 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0) 731 #define BS_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1 22 732 #define BM_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1 \ 733 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1) 734 #define BS_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0 24 735 #define BM_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0 \ 736 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0) 737 #define BS_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1 26 738 #define BM_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1 \ 739 SHIFT_U32(3, BS_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1) 740 #define BS_CCM_CCGR3_OCRAM 28 741 #define BM_CCM_CCGR3_OCRAM SHIFT_U32(3, BS_CCM_CCGR3_OCRAM) 742 #define BS_CCM_CCGR3_OPENVGAXICLK 30 743 #define BM_CCM_CCGR3_OPENVGAXICLK \ 744 SHIFT_U32(3, BS_CCM_CCGR3_OPENVGAXICLK) 745 746 #define BS_CCM_CCGR4_PCIE 0 747 #define BM_CCM_CCGR4_PCIE SHIFT_U32(3, BS_CCM_CCGR4_PCIE) 748 #define BS_CCM_CCGR4_PL301_MX6QFAST1_S133 8 749 #define BM_CCM_CCGR4_PL301_MX6QFAST1_S133 \ 750 SHIFT_U32(3, BS_CCM_CCGR4_PL301_MX6QFAST1_S133) 751 #define BS_CCM_CCGR4_PL301_MX6QPER1_BCH 12 752 #define BM_CCM_CCGR4_PL301_MX6QPER1_BCH \ 753 SHIFT_U32(3, BS_CCM_CCGR4_PL301_MX6QPER1_BCH) 754 #define BS_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE 14 755 #define BM_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE \ 756 SHIFT_U32(3, BS_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE) 757 #define BS_CCM_CCGR4_PWM1 16 758 #define BM_CCM_CCGR4_PWM1 \ 759 SHIFT_U32(3, BS_CCM_CCGR4_PWM1) 760 #define BS_CCM_CCGR4_PWM2 18 761 #define BM_CCM_CCGR4_PWM2 \ 762 SHIFT_U32(3, BS_CCM_CCGR4_PWM2) 763 #define BS_CCM_CCGR4_PWM3 20 764 #define BM_CCM_CCGR4_PWM3 \ 765 SHIFT_U32(3, BS_CCM_CCGR4_PWM3) 766 #define BS_CCM_CCGR4_PWM4 22 767 #define BM_CCM_CCGR4_PWM4 \ 768 SHIFT_U32(3, BS_CCM_CCGR4_PWM4) 769 #define BS_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB 24 770 #define BM_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB \ 771 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB) 772 #define BS_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH 26 773 #define BM_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH \ 774 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH) 775 #define BS_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO 28 776 #define BM_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO \ 777 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO) 778 #define BS_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB 30 779 #define BM_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB \ 780 SHIFT_U32(3, BS_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB) 781 782 #define BS_CCM_CCGR5_ROM 0 783 #define BM_CCM_CCGR5_ROM SHIFT_U32(3, BS_CCM_CCGR5_ROM) 784 #define BS_CCM_CCGR5_SATA 4 785 #define BM_CCM_CCGR5_SATA SHIFT_U32(3, BS_CCM_CCGR5_SATA) 786 #define BS_CCM_CCGR5_SDMA 6 787 #define BM_CCM_CCGR5_SDMA SHIFT_U32(3, BS_CCM_CCGR5_SDMA) 788 #define BS_CCM_CCGR5_SPBA 12 789 #define BM_CCM_CCGR5_SPBA SHIFT_U32(3, BS_CCM_CCGR5_SPBA) 790 #define BS_CCM_CCGR5_SPDIF 14 791 #define BM_CCM_CCGR5_SPDIF SHIFT_U32(3, BS_CCM_CCGR5_SPDIF) 792 #define BS_CCM_CCGR5_SSI1 18 793 #define BM_CCM_CCGR5_SSI1 SHIFT_U32(3, BS_CCM_CCGR5_SSI1) 794 #define BS_CCM_CCGR5_SSI2 20 795 #define BM_CCM_CCGR5_SSI2 SHIFT_U32(3, BS_CCM_CCGR5_SSI2) 796 #define BS_CCM_CCGR5_SSI3 22 797 #define BM_CCM_CCGR5_SSI3 SHIFT_U32(3, BS_CCM_CCGR5_SSI3) 798 #define BS_CCM_CCGR5_UART 24 799 #define BM_CCM_CCGR5_UART SHIFT_U32(3, BS_CCM_CCGR5_UART) 800 #define BS_CCM_CCGR5_UART_SERIAL 26 801 #define BM_CCM_CCGR5_UART_SERIAL SHIFT_U32(3, BS_CCM_CCGR5_UART_SERIAL) 802 803 #define BS_CCM_CCGR6_USBOH3 0 804 #define BM_CCM_CCGR6_USBOH3 SHIFT_U32(3, BS_CCM_CCGR6_USBOH3) 805 #define BS_CCM_CCGR6_USDHC1 2 806 #define BM_CCM_CCGR6_USDHC1 SHIFT_U32(3, BS_CCM_CCGR6_USDHC1) 807 #define BS_CCM_CCGR6_USDHC2 4 808 #define BM_CCM_CCGR6_USDHC2 SHIFT_U32(3, BS_CCM_CCGR6_USDHC2) 809 #define BS_CCM_CCGR6_USDHC3 6 810 #define BM_CCM_CCGR6_USDHC3 SHIFT_U32(3, BS_CCM_CCGR6_USDHC3) 811 #define BS_CCM_CCGR6_USDHC4 8 812 #define BM_CCM_CCGR6_USDHC4 SHIFT_U32(3, BS_CCM_CCGR6_USDHC4) 813 #define BS_CCM_CCGR6_EMI_SLOW 10 814 #define BM_CCM_CCGR6_EMI_SLOW SHIFT_U32(3, BS_CCM_CCGR6_EMI_SLOW) 815 #define BS_CCM_CCGR6_VDOAXICLK 12 816 #define BM_CCM_CCGR6_VDOAXICLK SHIFT_U32(3, BS_CCM_CCGR6_VDOAXICLK) 817 #define BS_CCM_CCGR6_I2C4_SERIAL 24 818 #define BM_CCM_CCGR6_I2C4_SERIAL SHIFT_U32(3, BS_CCM_CCGR6_I2C4_SERIAL) 819 820 /* 821 * Define Analog Macros and common bits 822 */ 823 #define BS_CCM_ANALOG_PLL_LOCK 31 824 #define BM_CCM_ANALOG_PLL_LOCK \ 825 BIT32(BS_CCM_ANALOG_PLL_LOCK) 826 #define BS_CCM_ANALOG_PLL_BYPASS 16 827 #define BM_CCM_ANALOG_PLL_BYPASS \ 828 BIT32(BS_CCM_ANALOG_PLL_BYPASS) 829 #define BS_CCM_ANALOG_PLL_BYPASS_CLK_SRC 14 830 #define BM_CCM_ANALOG_PLL_BYPASS_CLK_SRC \ 831 SHIFT_U32(0x3, BS_CCM_ANALOG_PLL_BYPASS_CLK_SRC) 832 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC(clk) \ 833 (SHIFT_U32(clk, BS_CCM_ANALOG_PLL_BYPASS_CLK_SRC) & \ 834 BM_CCM_ANALOG_PLL_BYPASS_CLK_SRC) 835 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_CLK24M 0x0 836 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_CLK1 0x1 837 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_CLK2 0x2 838 #define CCM_ANALOG_PLL_BYPASS_CLK_SRC_XOR 0x3 839 840 #define BS_CCM_ANALOG_PLL_ENABLE 13 841 #define BM_CCM_ANALOG_PLL_ENABLE BIT32(BS_CCM_ANALOG_PLL_ENABLE) 842 #define BS_CCM_ANALOG_PLL_POWERDOWN 12 843 #define BM_CCM_ANALOG_PLL_POWERDOWN BIT32(BS_CCM_ANALOG_PLL_POWERDOWN) 844 #define BS_CCM_ANALOG_PLL_DIV_SELECT 0 845 846 /* 847 * Specific Analog bits definition 848 */ 849 #define BS_CCM_ANALOG_PLL_ARM_PLL_SEL 19 850 #define BM_CCM_ANALOG_PLL_ARM_PLL_SEL BIT32(BS_CCM_ANALOG_PLL_ARM_PLL_SEL) 851 #define BS_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL 18 852 #define BM_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL \ 853 BIT32(BS_CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL) 854 #define BS_CCM_ANALOG_PLL_ARM_LVDS_SEL 17 855 #define BM_CCM_ANALOG_PLL_ARM_LVDS_SEL \ 856 BIT32(BS_CCM_ANALOG_PLL_ARM_LVDS_SEL) 857 #define BM_CCM_ANALOG_PLL_ARM_DIV_SELECT \ 858 SHIFT_U32(0x7F, BS_CCM_ANALOG_PLL_DIV_SELECT) 859 860 #endif /* __IMX6_CRM_H__ */ 861