1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef INTERNAL_I2C_DRIVER_H
9 #define INTERNAL_I2C_DRIVER_H
10 
11 #include <stdbool.h>
12 #include <stdint.h>
13 
14 #define I2C_POLLING_LIMIT (0x00100000U)
15 
16 typedef enum {
17     I2C_ERR_OK = 0,
18     I2C_ERR_PARAM,
19     I2C_ERR_BUSY,
20     I2C_ERR_BER,
21     I2C_ERR_BER_MC,
22     I2C_ERR_POLLING,
23     I2C_ERR_UNAVAILABLE
24 } I2C_ERR_t;
25 
26 typedef enum {
27     I2C_EN_EVF_NONE = 0,
28     I2C_EN_EVF_FINISH,
29     I2C_EN_EVF_BUSERROR,
30     I2C_EN_EVF_MC_BUSERROR,
31     I2C_EN_EVF_TIMEOUT,
32     I2C_EN_EVF_NAK
33 } I2C_EN_EVF_t;
34 
35 typedef enum { I2C_TYPE_F_I2C = 0, I2C_TYPE_F_I2C_SP1 } I2C_TYPE;
36 
37 typedef union {
38     uint8_t DATA;
39     struct {
40         /** B[0] READ/WRITE */
41         uint32_t BITFIELD_READ : 1;
42         /** B[7:1] TARGET ADDRESS */
43         uint32_t BITFIELD_ADDR : 7;
44     } bit;
45 } I2C_UN_SLVADDR_t;
46 
47 typedef union {
48     struct {
49         uint8_t FSR_FS;
50         uint8_t CSR_CS;
51         uint8_t CCR_CS;
52         uint8_t CCR_FM;
53     } I2C_PARAM_F_I2C;
54     struct {
55         uint8_t NFR_NF;
56         uint8_t NFR_NFH;
57         uint8_t TLWR_TLW;
58         uint8_t TLW2R_TLW;
59         uint8_t THWR_THW;
60         uint8_t THW2R_THW;
61         uint8_t TBFR_TBF;
62         uint8_t TBF2R_TBF;
63         uint8_t TRSR_TRS;
64         uint8_t TRS2R_TRS;
65         uint8_t TSHR_TSH;
66         uint8_t TSH2R_TSH;
67         uint8_t TPSR_TPS;
68         uint8_t TPS2R_TPS;
69         uint8_t TLWRH_TLWH;
70         uint8_t THWRH_THWH;
71         uint8_t TRSRH_TRSH;
72         uint8_t TSHRH_TSHH;
73         uint8_t TPSRH_TPSH;
74     } I2C_PARAM_F_I2C_SP1;
75 } I2C_PARAM_t;
76 
77 typedef struct {
78     char *BUFF;
79     bool *ATTR;
80     int SIZE;
81     int LIMIT;
82     int INDEX;
83 } I2C_ST_FIFO_t;
84 
85 typedef struct {
86     I2C_ST_FIFO_t CTRL;
87     I2C_ST_FIFO_t DATA;
88 } I2C_ST_PACKET_t;
89 
90 typedef struct {
91     I2C_TYPE TYPE;
92     uint32_t I2C_BASE_ADDR;
93     bool USE_HS_MODE;
94     bool CONTROLLER_CODE_FLAG;
95     I2C_ST_PACKET_t PACKET;
96     char CTRL_BUFF[0x08];
97     bool CTRL_ATTR[0x08];
98 } I2C_ST_PACKET_INFO_t;
99 
100 I2C_ST_PACKET_t *i2c_packet_initialize(I2C_ST_PACKET_t *packet);
101 
102 I2C_ST_PACKET_t *i2c_packet_set_payload(
103     I2C_ST_PACKET_t *packet,
104     char *buffer,
105     int size);
106 
107 I2C_ST_PACKET_t *i2c_packet_set_control(
108     I2C_ST_PACKET_t *packet,
109     uint32_t address,
110     bool read);
111 
112 I2C_ST_PACKET_t *i2c_packet_set_address(
113     I2C_ST_PACKET_t *packet,
114     int address,
115     int size);
116 
117 I2C_ERR_t i2c_handler_polling(I2C_ST_PACKET_INFO_t *packet_info);
118 
119 I2C_ERR_t i2c_initialize(
120     I2C_ST_PACKET_INFO_t *packet_info,
121     uint32_t reg_base,
122     I2C_TYPE type,
123     const I2C_PARAM_t *param);
124 
125 I2C_ERR_t i2c_exec_transfer(I2C_ST_PACKET_INFO_t *packet_info);
126 
127 void i2c_disable(I2C_ST_PACKET_INFO_t *packet);
128 
129 void i2c_enable(I2C_ST_PACKET_INFO_t *packet_info);
130 
131 #endif /* INTERNAL_I2C_DRIVER_H */
132