1 /*
2  * Copyright 2021 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef QSPI_H
9 #define QSPI_H
10 
11 #include <endian.h>
12 #include <lib/mmio.h>
13 
14 #define CHS_QSPI_MCR			0x01550000
15 #define CHS_QSPI_64LE			0xC
16 
17 #ifdef NXP_QSPI_BE
18 #define qspi_in32(a)           bswap32(mmio_read_32((uintptr_t)(a)))
19 #define qspi_out32(a, v)       mmio_write_32((uintptr_t)(a), bswap32(v))
20 #elif defined(NXP_QSPI_LE)
21 #define qspi_in32(a)           mmio_read_32((uintptr_t)(a))
22 #define qspi_out32(a, v)       mmio_write_32((uintptr_t)(a), (v))
23 #else
24 #error Please define CCSR QSPI register endianness
25 #endif
26 
27 int qspi_io_setup(uintptr_t nxp_qspi_flash_addr,
28 		  size_t nxp_qspi_flash_size,
29 		  uintptr_t fip_offset);
30 #endif /* __QSPI_H__ */
31