1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11
12 /*
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
16 *
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18 */
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
23 /* unused */
24 /* unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
35
36 struct clk;
37 struct clk_hw;
38 struct clk_core;
39 struct dentry;
40
41 /**
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
44 *
45 * Should be initialized by calling clk_hw_init_rate_request().
46 *
47 * @core: Pointer to the struct clk_core affected by this request
48 * @rate: Requested clock rate. This field will be adjusted by
49 * clock drivers according to hardware capabilities.
50 * @min_rate: Minimum rate imposed by clk users.
51 * @max_rate: Maximum rate imposed by clk users.
52 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
53 * requested constraints.
54 * @best_parent_hw: The most appropriate parent clock that fulfills the
55 * requested constraints.
56 *
57 */
58 struct clk_rate_request {
59 struct clk_core *core;
60 unsigned long rate;
61 unsigned long min_rate;
62 unsigned long max_rate;
63 unsigned long best_parent_rate;
64 struct clk_hw *best_parent_hw;
65 };
66
67 void clk_hw_init_rate_request(const struct clk_hw *hw,
68 struct clk_rate_request *req,
69 unsigned long rate);
70 void clk_hw_forward_rate_request(const struct clk_hw *core,
71 const struct clk_rate_request *old_req,
72 const struct clk_hw *parent,
73 struct clk_rate_request *req,
74 unsigned long parent_rate);
75
76 /**
77 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
78 *
79 * @num: Numerator of the duty cycle ratio
80 * @den: Denominator of the duty cycle ratio
81 */
82 struct clk_duty {
83 unsigned int num;
84 unsigned int den;
85 };
86
87 /**
88 * struct clk_ops - Callback operations for hardware clocks; these are to
89 * be provided by the clock implementation, and will be called by drivers
90 * through the clk_* api.
91 *
92 * @prepare: Prepare the clock for enabling. This must not return until
93 * the clock is fully prepared, and it's safe to call clk_enable.
94 * This callback is intended to allow clock implementations to
95 * do any initialisation that may sleep. Called with
96 * prepare_lock held.
97 *
98 * @unprepare: Release the clock from its prepared state. This will typically
99 * undo any work done in the @prepare callback. Called with
100 * prepare_lock held.
101 *
102 * @is_prepared: Queries the hardware to determine if the clock is prepared.
103 * This function is allowed to sleep. Optional, if this op is not
104 * set then the prepare count will be used.
105 *
106 * @unprepare_unused: Unprepare the clock atomically. Only called from
107 * clk_disable_unused for prepare clocks with special needs.
108 * Called with prepare mutex held. This function may sleep.
109 *
110 * @enable: Enable the clock atomically. This must not return until the
111 * clock is generating a valid clock signal, usable by consumer
112 * devices. Called with enable_lock held. This function must not
113 * sleep.
114 *
115 * @disable: Disable the clock atomically. Called with enable_lock held.
116 * This function must not sleep.
117 *
118 * @is_enabled: Queries the hardware to determine if the clock is enabled.
119 * This function must not sleep. Optional, if this op is not
120 * set then the enable count will be used.
121 *
122 * @disable_unused: Disable the clock atomically. Only called from
123 * clk_disable_unused for gate clocks with special needs.
124 * Called with enable_lock held. This function must not
125 * sleep.
126 *
127 * @save_context: Save the context of the clock in prepration for poweroff.
128 *
129 * @restore_context: Restore the context of the clock after a restoration
130 * of power.
131 *
132 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
133 * parent rate is an input parameter. It is up to the caller to
134 * ensure that the prepare_mutex is held across this call. If the
135 * driver cannot figure out a rate for this clock, it must return
136 * 0. Returns the calculated rate. Optional, but recommended - if
137 * this op is not set then clock rate will be initialized to 0.
138 *
139 * @round_rate: Given a target rate as input, returns the closest rate actually
140 * supported by the clock. The parent rate is an input/output
141 * parameter.
142 *
143 * @determine_rate: Given a target rate as input, returns the closest rate
144 * actually supported by the clock, and optionally the parent clock
145 * that should be used to provide the clock rate.
146 *
147 * @set_parent: Change the input source of this clock; for clocks with multiple
148 * possible parents specify a new parent by passing in the index
149 * as a u8 corresponding to the parent in either the .parent_names
150 * or .parents arrays. This function in affect translates an
151 * array index into the value programmed into the hardware.
152 * Returns 0 on success, -EERROR otherwise.
153 *
154 * @get_parent: Queries the hardware to determine the parent of a clock. The
155 * return value is a u8 which specifies the index corresponding to
156 * the parent clock. This index can be applied to either the
157 * .parent_names or .parents arrays. In short, this function
158 * translates the parent value read from hardware into an array
159 * index. Currently only called when the clock is initialized by
160 * __clk_init. This callback is mandatory for clocks with
161 * multiple parents. It is optional (and unnecessary) for clocks
162 * with 0 or 1 parents.
163 *
164 * @set_rate: Change the rate of this clock. The requested rate is specified
165 * by the second argument, which should typically be the return
166 * of .round_rate call. The third argument gives the parent rate
167 * which is likely helpful for most .set_rate implementation.
168 * Returns 0 on success, -EERROR otherwise.
169 *
170 * @set_rate_and_parent: Change the rate and the parent of this clock. The
171 * requested rate is specified by the second argument, which
172 * should typically be the return of .round_rate call. The
173 * third argument gives the parent rate which is likely helpful
174 * for most .set_rate_and_parent implementation. The fourth
175 * argument gives the parent index. This callback is optional (and
176 * unnecessary) for clocks with 0 or 1 parents as well as
177 * for clocks that can tolerate switching the rate and the parent
178 * separately via calls to .set_parent and .set_rate.
179 * Returns 0 on success, -EERROR otherwise.
180 *
181 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
182 * is expressed in ppb (parts per billion). The parent accuracy is
183 * an input parameter.
184 * Returns the calculated accuracy. Optional - if this op is not
185 * set then clock accuracy will be initialized to parent accuracy
186 * or 0 (perfect clock) if clock has no parent.
187 *
188 * @get_phase: Queries the hardware to get the current phase of a clock.
189 * Returned values are 0-359 degrees on success, negative
190 * error codes on failure.
191 *
192 * @set_phase: Shift the phase this clock signal in degrees specified
193 * by the second argument. Valid values for degrees are
194 * 0-359. Return 0 on success, otherwise -EERROR.
195 *
196 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
197 * of a clock. Returned values denominator cannot be 0 and must be
198 * superior or equal to the numerator.
199 *
200 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
201 * the numerator (2nd argurment) and denominator (3rd argument).
202 * Argument must be a valid ratio (denominator > 0
203 * and >= numerator) Return 0 on success, otherwise -EERROR.
204 *
205 * @init: Perform platform-specific initialization magic.
206 * This is not used by any of the basic clock types.
207 * This callback exist for HW which needs to perform some
208 * initialisation magic for CCF to get an accurate view of the
209 * clock. It may also be used dynamic resource allocation is
210 * required. It shall not used to deal with clock parameters,
211 * such as rate or parents.
212 * Returns 0 on success, -EERROR otherwise.
213 *
214 * @terminate: Free any resource allocated by init.
215 *
216 * @debug_init: Set up type-specific debugfs entries for this clock. This
217 * is called once, after the debugfs directory entry for this
218 * clock has been created. The dentry pointer representing that
219 * directory is provided as an argument. Called with
220 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
221 *
222 *
223 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
224 * implementations to split any work between atomic (enable) and sleepable
225 * (prepare) contexts. If enabling a clock requires code that might sleep,
226 * this must be done in clk_prepare. Clock enable code that will never be
227 * called in a sleepable context may be implemented in clk_enable.
228 *
229 * Typically, drivers will call clk_prepare when a clock may be needed later
230 * (eg. when a device is opened), and clk_enable when the clock is actually
231 * required (eg. from an interrupt). Note that clk_prepare MUST have been
232 * called before clk_enable.
233 */
234 struct clk_ops {
235 int (*prepare)(struct clk_hw *hw);
236 void (*unprepare)(struct clk_hw *hw);
237 int (*is_prepared)(struct clk_hw *hw);
238 void (*unprepare_unused)(struct clk_hw *hw);
239 int (*enable)(struct clk_hw *hw);
240 void (*disable)(struct clk_hw *hw);
241 int (*is_enabled)(struct clk_hw *hw);
242 void (*disable_unused)(struct clk_hw *hw);
243 int (*save_context)(struct clk_hw *hw);
244 void (*restore_context)(struct clk_hw *hw);
245 unsigned long (*recalc_rate)(struct clk_hw *hw,
246 unsigned long parent_rate);
247 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
248 unsigned long *parent_rate);
249 int (*determine_rate)(struct clk_hw *hw,
250 struct clk_rate_request *req);
251 int (*set_parent)(struct clk_hw *hw, u8 index);
252 u8 (*get_parent)(struct clk_hw *hw);
253 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
254 unsigned long parent_rate);
255 int (*set_rate_and_parent)(struct clk_hw *hw,
256 unsigned long rate,
257 unsigned long parent_rate, u8 index);
258 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
259 unsigned long parent_accuracy);
260 int (*get_phase)(struct clk_hw *hw);
261 int (*set_phase)(struct clk_hw *hw, int degrees);
262 int (*get_duty_cycle)(struct clk_hw *hw,
263 struct clk_duty *duty);
264 int (*set_duty_cycle)(struct clk_hw *hw,
265 struct clk_duty *duty);
266 int (*init)(struct clk_hw *hw);
267 void (*terminate)(struct clk_hw *hw);
268 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
269 };
270
271 /**
272 * struct clk_parent_data - clk parent information
273 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
274 * @fw_name: parent name local to provider registering clk
275 * @name: globally unique parent name (used as a fallback)
276 * @index: parent index local to provider registering clk (if @fw_name absent)
277 */
278 struct clk_parent_data {
279 const struct clk_hw *hw;
280 const char *fw_name;
281 const char *name;
282 int index;
283 };
284
285 /**
286 * struct clk_init_data - holds init data that's common to all clocks and is
287 * shared between the clock provider and the common clock framework.
288 *
289 * @name: clock name
290 * @ops: operations this clock supports
291 * @parent_names: array of string names for all possible parents
292 * @parent_data: array of parent data for all possible parents (when some
293 * parents are external to the clk controller)
294 * @parent_hws: array of pointers to all possible parents (when all parents
295 * are internal to the clk controller)
296 * @num_parents: number of possible parents
297 * @flags: framework-level hints and quirks
298 */
299 struct clk_init_data {
300 const char *name;
301 const struct clk_ops *ops;
302 /* Only one of the following three should be assigned */
303 const char * const *parent_names;
304 const struct clk_parent_data *parent_data;
305 const struct clk_hw **parent_hws;
306 u8 num_parents;
307 unsigned long flags;
308 };
309
310 /**
311 * struct clk_hw - handle for traversing from a struct clk to its corresponding
312 * hardware-specific structure. struct clk_hw should be declared within struct
313 * clk_foo and then referenced by the struct clk instance that uses struct
314 * clk_foo's clk_ops
315 *
316 * @core: pointer to the struct clk_core instance that points back to this
317 * struct clk_hw instance
318 *
319 * @clk: pointer to the per-user struct clk instance that can be used to call
320 * into the clk API
321 *
322 * @init: pointer to struct clk_init_data that contains the init data shared
323 * with the common clock framework. This pointer will be set to NULL once
324 * a clk_register() variant is called on this clk_hw pointer.
325 */
326 struct clk_hw {
327 struct clk_core *core;
328 struct clk *clk;
329 const struct clk_init_data *init;
330 };
331
332 /*
333 * DOC: Basic clock implementations common to many platforms
334 *
335 * Each basic clock hardware type is comprised of a structure describing the
336 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
337 * unique flags for that hardware type, a registration function and an
338 * alternative macro for static initialization
339 */
340
341 /**
342 * struct clk_fixed_rate - fixed-rate clock
343 * @hw: handle between common and hardware-specific interfaces
344 * @fixed_rate: constant frequency of clock
345 * @fixed_accuracy: constant accuracy of clock in ppb (parts per billion)
346 * @flags: hardware specific flags
347 *
348 * Flags:
349 * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
350 * instead of what's set in @fixed_accuracy.
351 */
352 struct clk_fixed_rate {
353 struct clk_hw hw;
354 unsigned long fixed_rate;
355 unsigned long fixed_accuracy;
356 unsigned long flags;
357 };
358
359 #define CLK_FIXED_RATE_PARENT_ACCURACY BIT(0)
360
361 extern const struct clk_ops clk_fixed_rate_ops;
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
363 struct device_node *np, const char *name,
364 const char *parent_name, const struct clk_hw *parent_hw,
365 const struct clk_parent_data *parent_data, unsigned long flags,
366 unsigned long fixed_rate, unsigned long fixed_accuracy,
367 unsigned long clk_fixed_flags, bool devm);
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
369 const char *parent_name, unsigned long flags,
370 unsigned long fixed_rate);
371 /**
372 * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
373 * framework
374 * @dev: device that is registering this clock
375 * @name: name of this clock
376 * @parent_name: name of clock's parent
377 * @flags: framework-specific flags
378 * @fixed_rate: non-adjustable clock rate
379 */
380 #define clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
381 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
382 NULL, (flags), (fixed_rate), 0, 0, false)
383
384 /**
385 * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
386 * framework
387 * @dev: device that is registering this clock
388 * @name: name of this clock
389 * @parent_name: name of clock's parent
390 * @flags: framework-specific flags
391 * @fixed_rate: non-adjustable clock rate
392 */
393 #define devm_clk_hw_register_fixed_rate(dev, name, parent_name, flags, fixed_rate) \
394 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), NULL, \
395 NULL, (flags), (fixed_rate), 0, 0, true)
396 /**
397 * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
398 * the clock framework
399 * @dev: device that is registering this clock
400 * @name: name of this clock
401 * @parent_hw: pointer to parent clk
402 * @flags: framework-specific flags
403 * @fixed_rate: non-adjustable clock rate
404 */
405 #define clk_hw_register_fixed_rate_parent_hw(dev, name, parent_hw, flags, \
406 fixed_rate) \
407 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw), \
408 NULL, (flags), (fixed_rate), 0, 0, false)
409 /**
410 * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
411 * the clock framework
412 * @dev: device that is registering this clock
413 * @name: name of this clock
414 * @parent_data: parent clk data
415 * @flags: framework-specific flags
416 * @fixed_rate: non-adjustable clock rate
417 */
418 #define clk_hw_register_fixed_rate_parent_data(dev, name, parent_hw, flags, \
419 fixed_rate) \
420 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
421 (parent_data), (flags), (fixed_rate), 0, \
422 0, false)
423 /**
424 * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
425 * the clock framework
426 * @dev: device that is registering this clock
427 * @name: name of this clock
428 * @parent_name: name of clock's parent
429 * @flags: framework-specific flags
430 * @fixed_rate: non-adjustable clock rate
431 * @fixed_accuracy: non-adjustable clock accuracy
432 */
433 #define clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name, \
434 flags, fixed_rate, \
435 fixed_accuracy) \
436 __clk_hw_register_fixed_rate((dev), NULL, (name), (parent_name), \
437 NULL, NULL, (flags), (fixed_rate), \
438 (fixed_accuracy), 0, false)
439 /**
440 * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
441 * clock with the clock framework
442 * @dev: device that is registering this clock
443 * @name: name of this clock
444 * @parent_hw: pointer to parent clk
445 * @flags: framework-specific flags
446 * @fixed_rate: non-adjustable clock rate
447 * @fixed_accuracy: non-adjustable clock accuracy
448 */
449 #define clk_hw_register_fixed_rate_with_accuracy_parent_hw(dev, name, \
450 parent_hw, flags, fixed_rate, fixed_accuracy) \
451 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, (parent_hw) \
452 NULL, NULL, (flags), (fixed_rate), \
453 (fixed_accuracy), 0, false)
454 /**
455 * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
456 * clock with the clock framework
457 * @dev: device that is registering this clock
458 * @name: name of this clock
459 * @parent_name: name of clock's parent
460 * @flags: framework-specific flags
461 * @fixed_rate: non-adjustable clock rate
462 * @fixed_accuracy: non-adjustable clock accuracy
463 */
464 #define clk_hw_register_fixed_rate_with_accuracy_parent_data(dev, name, \
465 parent_data, flags, fixed_rate, fixed_accuracy) \
466 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
467 (parent_data), NULL, (flags), \
468 (fixed_rate), (fixed_accuracy), 0, false)
469 /**
470 * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
471 * the clock framework
472 * @dev: device that is registering this clock
473 * @name: name of this clock
474 * @parent_name: name of clock's parent
475 * @flags: framework-specific flags
476 * @fixed_rate: non-adjustable clock rate
477 */
478 #define clk_hw_register_fixed_rate_parent_accuracy(dev, name, parent_data, \
479 flags, fixed_rate) \
480 __clk_hw_register_fixed_rate((dev), NULL, (name), NULL, NULL, \
481 (parent_data), (flags), (fixed_rate), 0, \
482 CLK_FIXED_RATE_PARENT_ACCURACY, false)
483
484 void clk_unregister_fixed_rate(struct clk *clk);
485 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
486
487 void of_fixed_clk_setup(struct device_node *np);
488
489 /**
490 * struct clk_gate - gating clock
491 *
492 * @hw: handle between common and hardware-specific interfaces
493 * @reg: register controlling gate
494 * @bit_idx: single bit controlling gate
495 * @flags: hardware-specific flags
496 * @lock: register lock
497 *
498 * Clock which can gate its output. Implements .enable & .disable
499 *
500 * Flags:
501 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
502 * enable the clock. Setting this flag does the opposite: setting the bit
503 * disable the clock and clearing it enables the clock
504 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
505 * of this register, and mask of gate bits are in higher 16-bit of this
506 * register. While setting the gate bits, higher 16-bit should also be
507 * updated to indicate changing gate bits.
508 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
509 * the gate register. Setting this flag makes the register accesses big
510 * endian.
511 */
512 struct clk_gate {
513 struct clk_hw hw;
514 void __iomem *reg;
515 u8 bit_idx;
516 u8 flags;
517 spinlock_t *lock;
518 };
519
520 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
521
522 #define CLK_GATE_SET_TO_DISABLE BIT(0)
523 #define CLK_GATE_HIWORD_MASK BIT(1)
524 #define CLK_GATE_BIG_ENDIAN BIT(2)
525
526 extern const struct clk_ops clk_gate_ops;
527 struct clk_hw *__clk_hw_register_gate(struct device *dev,
528 struct device_node *np, const char *name,
529 const char *parent_name, const struct clk_hw *parent_hw,
530 const struct clk_parent_data *parent_data,
531 unsigned long flags,
532 void __iomem *reg, u8 bit_idx,
533 u8 clk_gate_flags, spinlock_t *lock);
534 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
535 struct device_node *np, const char *name,
536 const char *parent_name, const struct clk_hw *parent_hw,
537 const struct clk_parent_data *parent_data,
538 unsigned long flags,
539 void __iomem *reg, u8 bit_idx,
540 u8 clk_gate_flags, spinlock_t *lock);
541 struct clk *clk_register_gate(struct device *dev, const char *name,
542 const char *parent_name, unsigned long flags,
543 void __iomem *reg, u8 bit_idx,
544 u8 clk_gate_flags, spinlock_t *lock);
545 /**
546 * clk_hw_register_gate - register a gate clock with the clock framework
547 * @dev: device that is registering this clock
548 * @name: name of this clock
549 * @parent_name: name of this clock's parent
550 * @flags: framework-specific flags for this clock
551 * @reg: register address to control gating of this clock
552 * @bit_idx: which bit in the register controls gating of this clock
553 * @clk_gate_flags: gate-specific flags for this clock
554 * @lock: shared register lock for this clock
555 */
556 #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx, \
557 clk_gate_flags, lock) \
558 __clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
559 NULL, (flags), (reg), (bit_idx), \
560 (clk_gate_flags), (lock))
561 /**
562 * clk_hw_register_gate_parent_hw - register a gate clock with the clock
563 * framework
564 * @dev: device that is registering this clock
565 * @name: name of this clock
566 * @parent_hw: pointer to parent clk
567 * @flags: framework-specific flags for this clock
568 * @reg: register address to control gating of this clock
569 * @bit_idx: which bit in the register controls gating of this clock
570 * @clk_gate_flags: gate-specific flags for this clock
571 * @lock: shared register lock for this clock
572 */
573 #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg, \
574 bit_idx, clk_gate_flags, lock) \
575 __clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw), \
576 NULL, (flags), (reg), (bit_idx), \
577 (clk_gate_flags), (lock))
578 /**
579 * clk_hw_register_gate_parent_data - register a gate clock with the clock
580 * framework
581 * @dev: device that is registering this clock
582 * @name: name of this clock
583 * @parent_data: parent clk data
584 * @flags: framework-specific flags for this clock
585 * @reg: register address to control gating of this clock
586 * @bit_idx: which bit in the register controls gating of this clock
587 * @clk_gate_flags: gate-specific flags for this clock
588 * @lock: shared register lock for this clock
589 */
590 #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg, \
591 bit_idx, clk_gate_flags, lock) \
592 __clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
593 (flags), (reg), (bit_idx), \
594 (clk_gate_flags), (lock))
595 /**
596 * devm_clk_hw_register_gate - register a gate clock with the clock framework
597 * @dev: device that is registering this clock
598 * @name: name of this clock
599 * @parent_name: name of this clock's parent
600 * @flags: framework-specific flags for this clock
601 * @reg: register address to control gating of this clock
602 * @bit_idx: which bit in the register controls gating of this clock
603 * @clk_gate_flags: gate-specific flags for this clock
604 * @lock: shared register lock for this clock
605 */
606 #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
607 clk_gate_flags, lock) \
608 __devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
609 NULL, (flags), (reg), (bit_idx), \
610 (clk_gate_flags), (lock))
611 void clk_unregister_gate(struct clk *clk);
612 void clk_hw_unregister_gate(struct clk_hw *hw);
613 int clk_gate_is_enabled(struct clk_hw *hw);
614
615 struct clk_div_table {
616 unsigned int val;
617 unsigned int div;
618 };
619
620 /**
621 * struct clk_divider - adjustable divider clock
622 *
623 * @hw: handle between common and hardware-specific interfaces
624 * @reg: register containing the divider
625 * @shift: shift to the divider bit field
626 * @width: width of the divider bit field
627 * @table: array of value/divider pairs, last entry should have div = 0
628 * @lock: register lock
629 *
630 * Clock with an adjustable divider affecting its output frequency. Implements
631 * .recalc_rate, .set_rate and .round_rate
632 *
633 * Flags:
634 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
635 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
636 * the raw value read from the register, with the value of zero considered
637 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
638 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
639 * the hardware register
640 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
641 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
642 * Some hardware implementations gracefully handle this case and allow a
643 * zero divisor by not modifying their input clock
644 * (divide by one / bypass).
645 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
646 * of this register, and mask of divider bits are in higher 16-bit of this
647 * register. While setting the divider bits, higher 16-bit should also be
648 * updated to indicate changing divider bits.
649 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
650 * to the closest integer instead of the up one.
651 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
652 * not be changed by the clock framework.
653 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
654 * except when the value read from the register is zero, the divisor is
655 * 2^width of the field.
656 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
657 * for the divider register. Setting this flag makes the register accesses
658 * big endian.
659 */
660 struct clk_divider {
661 struct clk_hw hw;
662 void __iomem *reg;
663 u8 shift;
664 u8 width;
665 u8 flags;
666 const struct clk_div_table *table;
667 spinlock_t *lock;
668 };
669
670 #define clk_div_mask(width) ((1 << (width)) - 1)
671 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
672
673 #define CLK_DIVIDER_ONE_BASED BIT(0)
674 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
675 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
676 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
677 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
678 #define CLK_DIVIDER_READ_ONLY BIT(5)
679 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
680 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
681
682 extern const struct clk_ops clk_divider_ops;
683 extern const struct clk_ops clk_divider_ro_ops;
684
685 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
686 unsigned int val, const struct clk_div_table *table,
687 unsigned long flags, unsigned long width);
688 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
689 unsigned long rate, unsigned long *prate,
690 const struct clk_div_table *table,
691 u8 width, unsigned long flags);
692 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
693 unsigned long rate, unsigned long *prate,
694 const struct clk_div_table *table, u8 width,
695 unsigned long flags, unsigned int val);
696 int divider_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
697 const struct clk_div_table *table, u8 width,
698 unsigned long flags);
699 int divider_ro_determine_rate(struct clk_hw *hw, struct clk_rate_request *req,
700 const struct clk_div_table *table, u8 width,
701 unsigned long flags, unsigned int val);
702 int divider_get_val(unsigned long rate, unsigned long parent_rate,
703 const struct clk_div_table *table, u8 width,
704 unsigned long flags);
705
706 struct clk_hw *__clk_hw_register_divider(struct device *dev,
707 struct device_node *np, const char *name,
708 const char *parent_name, const struct clk_hw *parent_hw,
709 const struct clk_parent_data *parent_data, unsigned long flags,
710 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
711 const struct clk_div_table *table, spinlock_t *lock);
712 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
713 struct device_node *np, const char *name,
714 const char *parent_name, const struct clk_hw *parent_hw,
715 const struct clk_parent_data *parent_data, unsigned long flags,
716 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
717 const struct clk_div_table *table, spinlock_t *lock);
718 struct clk *clk_register_divider_table(struct device *dev, const char *name,
719 const char *parent_name, unsigned long flags,
720 void __iomem *reg, u8 shift, u8 width,
721 u8 clk_divider_flags, const struct clk_div_table *table,
722 spinlock_t *lock);
723 /**
724 * clk_register_divider - register a divider clock with the clock framework
725 * @dev: device registering this clock
726 * @name: name of this clock
727 * @parent_name: name of clock's parent
728 * @flags: framework-specific flags
729 * @reg: register address to adjust divider
730 * @shift: number of bits to shift the bitfield
731 * @width: width of the bitfield
732 * @clk_divider_flags: divider-specific flags for this clock
733 * @lock: shared register lock for this clock
734 */
735 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \
736 clk_divider_flags, lock) \
737 clk_register_divider_table((dev), (name), (parent_name), (flags), \
738 (reg), (shift), (width), \
739 (clk_divider_flags), NULL, (lock))
740 /**
741 * clk_hw_register_divider - register a divider clock with the clock framework
742 * @dev: device registering this clock
743 * @name: name of this clock
744 * @parent_name: name of clock's parent
745 * @flags: framework-specific flags
746 * @reg: register address to adjust divider
747 * @shift: number of bits to shift the bitfield
748 * @width: width of the bitfield
749 * @clk_divider_flags: divider-specific flags for this clock
750 * @lock: shared register lock for this clock
751 */
752 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
753 width, clk_divider_flags, lock) \
754 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
755 NULL, (flags), (reg), (shift), (width), \
756 (clk_divider_flags), NULL, (lock))
757 /**
758 * clk_hw_register_divider_parent_hw - register a divider clock with the clock
759 * framework
760 * @dev: device registering this clock
761 * @name: name of this clock
762 * @parent_hw: pointer to parent clk
763 * @flags: framework-specific flags
764 * @reg: register address to adjust divider
765 * @shift: number of bits to shift the bitfield
766 * @width: width of the bitfield
767 * @clk_divider_flags: divider-specific flags for this clock
768 * @lock: shared register lock for this clock
769 */
770 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, \
771 shift, width, clk_divider_flags, \
772 lock) \
773 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
774 NULL, (flags), (reg), (shift), (width), \
775 (clk_divider_flags), NULL, (lock))
776 /**
777 * clk_hw_register_divider_parent_data - register a divider clock with the clock
778 * framework
779 * @dev: device registering this clock
780 * @name: name of this clock
781 * @parent_data: parent clk data
782 * @flags: framework-specific flags
783 * @reg: register address to adjust divider
784 * @shift: number of bits to shift the bitfield
785 * @width: width of the bitfield
786 * @clk_divider_flags: divider-specific flags for this clock
787 * @lock: shared register lock for this clock
788 */
789 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, \
790 reg, shift, width, \
791 clk_divider_flags, lock) \
792 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
793 (parent_data), (flags), (reg), (shift), \
794 (width), (clk_divider_flags), NULL, (lock))
795 /**
796 * clk_hw_register_divider_table - register a table based divider clock with
797 * the clock framework
798 * @dev: device registering this clock
799 * @name: name of this clock
800 * @parent_name: name of clock's parent
801 * @flags: framework-specific flags
802 * @reg: register address to adjust divider
803 * @shift: number of bits to shift the bitfield
804 * @width: width of the bitfield
805 * @clk_divider_flags: divider-specific flags for this clock
806 * @table: array of divider/value pairs ending with a div set to 0
807 * @lock: shared register lock for this clock
808 */
809 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, \
810 shift, width, clk_divider_flags, table, \
811 lock) \
812 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
813 NULL, (flags), (reg), (shift), (width), \
814 (clk_divider_flags), (table), (lock))
815 /**
816 * clk_hw_register_divider_table_parent_hw - register a table based divider
817 * clock with the clock framework
818 * @dev: device registering this clock
819 * @name: name of this clock
820 * @parent_hw: pointer to parent clk
821 * @flags: framework-specific flags
822 * @reg: register address to adjust divider
823 * @shift: number of bits to shift the bitfield
824 * @width: width of the bitfield
825 * @clk_divider_flags: divider-specific flags for this clock
826 * @table: array of divider/value pairs ending with a div set to 0
827 * @lock: shared register lock for this clock
828 */
829 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, \
830 reg, shift, width, \
831 clk_divider_flags, table, \
832 lock) \
833 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), \
834 NULL, (flags), (reg), (shift), (width), \
835 (clk_divider_flags), (table), (lock))
836 /**
837 * clk_hw_register_divider_table_parent_data - register a table based divider
838 * clock with the clock framework
839 * @dev: device registering this clock
840 * @name: name of this clock
841 * @parent_data: parent clk data
842 * @flags: framework-specific flags
843 * @reg: register address to adjust divider
844 * @shift: number of bits to shift the bitfield
845 * @width: width of the bitfield
846 * @clk_divider_flags: divider-specific flags for this clock
847 * @table: array of divider/value pairs ending with a div set to 0
848 * @lock: shared register lock for this clock
849 */
850 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, \
851 flags, reg, shift, width, \
852 clk_divider_flags, table, \
853 lock) \
854 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, \
855 (parent_data), (flags), (reg), (shift), \
856 (width), (clk_divider_flags), (table), \
857 (lock))
858 /**
859 * devm_clk_hw_register_divider - register a divider clock with the clock framework
860 * @dev: device registering this clock
861 * @name: name of this clock
862 * @parent_name: name of clock's parent
863 * @flags: framework-specific flags
864 * @reg: register address to adjust divider
865 * @shift: number of bits to shift the bitfield
866 * @width: width of the bitfield
867 * @clk_divider_flags: divider-specific flags for this clock
868 * @lock: shared register lock for this clock
869 */
870 #define devm_clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, \
871 width, clk_divider_flags, lock) \
872 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, \
873 NULL, (flags), (reg), (shift), (width), \
874 (clk_divider_flags), NULL, (lock))
875 /**
876 * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
877 * @dev: device registering this clock
878 * @name: name of this clock
879 * @parent_hw: pointer to parent clk
880 * @flags: framework-specific flags
881 * @reg: register address to adjust divider
882 * @shift: number of bits to shift the bitfield
883 * @width: width of the bitfield
884 * @clk_divider_flags: divider-specific flags for this clock
885 * @lock: shared register lock for this clock
886 */
887 #define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
888 reg, shift, width, \
889 clk_divider_flags, lock) \
890 __devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
891 (parent_hw), NULL, (flags), (reg), \
892 (shift), (width), (clk_divider_flags), \
893 NULL, (lock))
894 /**
895 * devm_clk_hw_register_divider_table - register a table based divider clock
896 * with the clock framework (devres variant)
897 * @dev: device registering this clock
898 * @name: name of this clock
899 * @parent_name: name of clock's parent
900 * @flags: framework-specific flags
901 * @reg: register address to adjust divider
902 * @shift: number of bits to shift the bitfield
903 * @width: width of the bitfield
904 * @clk_divider_flags: divider-specific flags for this clock
905 * @table: array of divider/value pairs ending with a div set to 0
906 * @lock: shared register lock for this clock
907 */
908 #define devm_clk_hw_register_divider_table(dev, name, parent_name, flags, \
909 reg, shift, width, \
910 clk_divider_flags, table, lock) \
911 __devm_clk_hw_register_divider((dev), NULL, (name), (parent_name), \
912 NULL, NULL, (flags), (reg), (shift), \
913 (width), (clk_divider_flags), (table), \
914 (lock))
915
916 void clk_unregister_divider(struct clk *clk);
917 void clk_hw_unregister_divider(struct clk_hw *hw);
918
919 /**
920 * struct clk_mux - multiplexer clock
921 *
922 * @hw: handle between common and hardware-specific interfaces
923 * @reg: register controlling multiplexer
924 * @table: array of register values corresponding to the parent index
925 * @shift: shift to multiplexer bit field
926 * @mask: mask of mutliplexer bit field
927 * @flags: hardware-specific flags
928 * @lock: register lock
929 *
930 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
931 * and .recalc_rate
932 *
933 * Flags:
934 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
935 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
936 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
937 * register, and mask of mux bits are in higher 16-bit of this register.
938 * While setting the mux bits, higher 16-bit should also be updated to
939 * indicate changing mux bits.
940 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
941 * .get_parent clk_op.
942 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
943 * frequency.
944 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
945 * the mux register. Setting this flag makes the register accesses big
946 * endian.
947 */
948 struct clk_mux {
949 struct clk_hw hw;
950 void __iomem *reg;
951 const u32 *table;
952 u32 mask;
953 u8 shift;
954 u8 flags;
955 spinlock_t *lock;
956 };
957
958 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
959
960 #define CLK_MUX_INDEX_ONE BIT(0)
961 #define CLK_MUX_INDEX_BIT BIT(1)
962 #define CLK_MUX_HIWORD_MASK BIT(2)
963 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
964 #define CLK_MUX_ROUND_CLOSEST BIT(4)
965 #define CLK_MUX_BIG_ENDIAN BIT(5)
966
967 extern const struct clk_ops clk_mux_ops;
968 extern const struct clk_ops clk_mux_ro_ops;
969
970 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
971 const char *name, u8 num_parents,
972 const char * const *parent_names,
973 const struct clk_hw **parent_hws,
974 const struct clk_parent_data *parent_data,
975 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
976 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
977 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
978 const char *name, u8 num_parents,
979 const char * const *parent_names,
980 const struct clk_hw **parent_hws,
981 const struct clk_parent_data *parent_data,
982 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
983 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
984 struct clk *clk_register_mux_table(struct device *dev, const char *name,
985 const char * const *parent_names, u8 num_parents,
986 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
987 u8 clk_mux_flags, const u32 *table, spinlock_t *lock);
988
989 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, \
990 shift, width, clk_mux_flags, lock) \
991 clk_register_mux_table((dev), (name), (parent_names), (num_parents), \
992 (flags), (reg), (shift), BIT((width)) - 1, \
993 (clk_mux_flags), NULL, (lock))
994 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, \
995 flags, reg, shift, mask, clk_mux_flags, \
996 table, lock) \
997 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
998 (parent_names), NULL, NULL, (flags), (reg), \
999 (shift), (mask), (clk_mux_flags), (table), \
1000 (lock))
1001 #define clk_hw_register_mux_table_parent_data(dev, name, parent_data, \
1002 num_parents, flags, reg, shift, mask, \
1003 clk_mux_flags, table, lock) \
1004 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1005 NULL, NULL, (parent_data), (flags), (reg), \
1006 (shift), (mask), (clk_mux_flags), (table), \
1007 (lock))
1008 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1009 shift, width, clk_mux_flags, lock) \
1010 __clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1011 (parent_names), NULL, NULL, (flags), (reg), \
1012 (shift), BIT((width)) - 1, (clk_mux_flags), \
1013 NULL, (lock))
1014 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, \
1015 reg, shift, width, clk_mux_flags, lock) \
1016 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1017 (parent_hws), NULL, (flags), (reg), (shift), \
1018 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1019 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, \
1020 flags, reg, shift, width, \
1021 clk_mux_flags, lock) \
1022 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1023 (parent_data), (flags), (reg), (shift), \
1024 BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1025 #define clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1026 num_parents, flags, reg, shift, \
1027 width, clk_mux_flags, table, \
1028 lock) \
1029 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, \
1030 (parent_data), (flags), (reg), (shift), \
1031 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1032 #define devm_clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, \
1033 shift, width, clk_mux_flags, lock) \
1034 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), \
1035 (parent_names), NULL, NULL, (flags), (reg), \
1036 (shift), BIT((width)) - 1, (clk_mux_flags), \
1037 NULL, (lock))
1038 #define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
1039 num_parents, flags, reg, shift, \
1040 width, clk_mux_flags, lock) \
1041 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1042 (parent_hws), NULL, (flags), (reg), \
1043 (shift), BIT((width)) - 1, \
1044 (clk_mux_flags), NULL, (lock))
1045 #define devm_clk_hw_register_mux_parent_data_table(dev, name, parent_data, \
1046 num_parents, flags, reg, shift, \
1047 width, clk_mux_flags, table, \
1048 lock) \
1049 __devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
1050 NULL, (parent_data), (flags), (reg), (shift), \
1051 BIT((width)) - 1, (clk_mux_flags), table, (lock))
1052
1053 int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
1054 unsigned int val);
1055 unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index);
1056
1057 void clk_unregister_mux(struct clk *clk);
1058 void clk_hw_unregister_mux(struct clk_hw *hw);
1059
1060 void of_fixed_factor_clk_setup(struct device_node *node);
1061
1062 /**
1063 * struct clk_fixed_factor - fixed multiplier and divider clock
1064 *
1065 * @hw: handle between common and hardware-specific interfaces
1066 * @mult: multiplier
1067 * @div: divider
1068 *
1069 * Clock with a fixed multiplier and divider. The output frequency is the
1070 * parent clock rate divided by div and multiplied by mult.
1071 * Implements .recalc_rate, .set_rate and .round_rate
1072 */
1073
1074 struct clk_fixed_factor {
1075 struct clk_hw hw;
1076 unsigned int mult;
1077 unsigned int div;
1078 };
1079
1080 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
1081
1082 extern const struct clk_ops clk_fixed_factor_ops;
1083 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1084 const char *parent_name, unsigned long flags,
1085 unsigned int mult, unsigned int div);
1086 void clk_unregister_fixed_factor(struct clk *clk);
1087 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1088 const char *name, const char *parent_name, unsigned long flags,
1089 unsigned int mult, unsigned int div);
1090 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
1091 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1092 const char *name, const char *parent_name, unsigned long flags,
1093 unsigned int mult, unsigned int div);
1094 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1095 const char *name, unsigned int index, unsigned long flags,
1096 unsigned int mult, unsigned int div);
1097
1098 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1099 const char *name, const struct clk_hw *parent_hw,
1100 unsigned long flags, unsigned int mult, unsigned int div);
1101
1102 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1103 const char *name, const struct clk_hw *parent_hw,
1104 unsigned long flags, unsigned int mult, unsigned int div);
1105 /**
1106 * struct clk_fractional_divider - adjustable fractional divider clock
1107 *
1108 * @hw: handle between common and hardware-specific interfaces
1109 * @reg: register containing the divider
1110 * @mshift: shift to the numerator bit field
1111 * @mwidth: width of the numerator bit field
1112 * @nshift: shift to the denominator bit field
1113 * @nwidth: width of the denominator bit field
1114 * @lock: register lock
1115 *
1116 * Clock with adjustable fractional divider affecting its output frequency.
1117 *
1118 * Flags:
1119 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1120 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
1121 * is set then the numerator and denominator are both the value read
1122 * plus one.
1123 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1124 * used for the divider register. Setting this flag makes the register
1125 * accesses big endian.
1126 * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1127 * be saturated and the caller will get quite far from the good enough
1128 * approximation. Instead the caller may require, by setting this flag,
1129 * to shift left by a few bits in case, when the asked one is quite small
1130 * to satisfy the desired range of denominator. It assumes that on the
1131 * caller's side the power-of-two capable prescaler exists.
1132 */
1133 struct clk_fractional_divider {
1134 struct clk_hw hw;
1135 void __iomem *reg;
1136 u8 mshift;
1137 u8 mwidth;
1138 u32 mmask;
1139 u8 nshift;
1140 u8 nwidth;
1141 u32 nmask;
1142 u8 flags;
1143 void (*approximation)(struct clk_hw *hw,
1144 unsigned long rate, unsigned long *parent_rate,
1145 unsigned long *m, unsigned long *n);
1146 spinlock_t *lock;
1147 };
1148
1149 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
1150
1151 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
1152 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
1153 #define CLK_FRAC_DIVIDER_POWER_OF_TWO_PS BIT(2)
1154
1155 struct clk *clk_register_fractional_divider(struct device *dev,
1156 const char *name, const char *parent_name, unsigned long flags,
1157 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1158 u8 clk_divider_flags, spinlock_t *lock);
1159 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1160 const char *name, const char *parent_name, unsigned long flags,
1161 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
1162 u8 clk_divider_flags, spinlock_t *lock);
1163 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
1164
1165 /**
1166 * struct clk_multiplier - adjustable multiplier clock
1167 *
1168 * @hw: handle between common and hardware-specific interfaces
1169 * @reg: register containing the multiplier
1170 * @shift: shift to the multiplier bit field
1171 * @width: width of the multiplier bit field
1172 * @lock: register lock
1173 *
1174 * Clock with an adjustable multiplier affecting its output frequency.
1175 * Implements .recalc_rate, .set_rate and .round_rate
1176 *
1177 * Flags:
1178 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1179 * from the register, with 0 being a valid value effectively
1180 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
1181 * set, then a null multiplier will be considered as a bypass,
1182 * leaving the parent rate unmodified.
1183 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1184 * rounded to the closest integer instead of the down one.
1185 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1186 * used for the multiplier register. Setting this flag makes the register
1187 * accesses big endian.
1188 */
1189 struct clk_multiplier {
1190 struct clk_hw hw;
1191 void __iomem *reg;
1192 u8 shift;
1193 u8 width;
1194 u8 flags;
1195 spinlock_t *lock;
1196 };
1197
1198 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
1199
1200 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
1201 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
1202 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
1203
1204 extern const struct clk_ops clk_multiplier_ops;
1205
1206 /***
1207 * struct clk_composite - aggregate clock of mux, divider and gate clocks
1208 *
1209 * @hw: handle between common and hardware-specific interfaces
1210 * @mux_hw: handle between composite and hardware-specific mux clock
1211 * @rate_hw: handle between composite and hardware-specific rate clock
1212 * @gate_hw: handle between composite and hardware-specific gate clock
1213 * @mux_ops: clock ops for mux
1214 * @rate_ops: clock ops for rate
1215 * @gate_ops: clock ops for gate
1216 */
1217 struct clk_composite {
1218 struct clk_hw hw;
1219 struct clk_ops ops;
1220
1221 struct clk_hw *mux_hw;
1222 struct clk_hw *rate_hw;
1223 struct clk_hw *gate_hw;
1224
1225 const struct clk_ops *mux_ops;
1226 const struct clk_ops *rate_ops;
1227 const struct clk_ops *gate_ops;
1228 };
1229
1230 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
1231
1232 struct clk *clk_register_composite(struct device *dev, const char *name,
1233 const char * const *parent_names, int num_parents,
1234 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1235 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1236 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1237 unsigned long flags);
1238 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1239 const struct clk_parent_data *parent_data, int num_parents,
1240 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1241 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1242 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1243 unsigned long flags);
1244 void clk_unregister_composite(struct clk *clk);
1245 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1246 const char * const *parent_names, int num_parents,
1247 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1248 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1249 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1250 unsigned long flags);
1251 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1252 const char *name,
1253 const struct clk_parent_data *parent_data, int num_parents,
1254 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1255 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1256 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1257 unsigned long flags);
1258 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1259 const char *name, const struct clk_parent_data *parent_data,
1260 int num_parents,
1261 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
1262 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
1263 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
1264 unsigned long flags);
1265 void clk_hw_unregister_composite(struct clk_hw *hw);
1266
1267 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1268 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1269
1270 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1271 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1272 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1273
1274 void clk_unregister(struct clk *clk);
1275
1276 void clk_hw_unregister(struct clk_hw *hw);
1277
1278 /* helper functions */
1279 const char *__clk_get_name(const struct clk *clk);
1280 const char *clk_hw_get_name(const struct clk_hw *hw);
1281 #ifdef CONFIG_COMMON_CLK
1282 struct clk_hw *__clk_get_hw(struct clk *clk);
1283 #else
__clk_get_hw(struct clk * clk)1284 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
1285 {
1286 return (struct clk_hw *)clk;
1287 }
1288 #endif
1289
1290 struct clk *clk_hw_get_clk(struct clk_hw *hw, const char *con_id);
1291 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1292 const char *con_id);
1293
1294 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
1295 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
1296 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
1297 unsigned int index);
1298 int clk_hw_get_parent_index(struct clk_hw *hw);
1299 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
1300 unsigned int __clk_get_enable_count(struct clk *clk);
1301 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
1302 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
1303 #define clk_hw_can_set_rate_parent(hw) \
1304 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
1305
1306 bool clk_hw_is_prepared(const struct clk_hw *hw);
1307 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
1308 bool clk_hw_is_enabled(const struct clk_hw *hw);
1309 bool __clk_is_enabled(struct clk *clk);
1310 struct clk *__clk_lookup(const char *name);
1311 int __clk_mux_determine_rate(struct clk_hw *hw,
1312 struct clk_rate_request *req);
1313 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
1314 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
1315 struct clk_rate_request *req);
1316 int clk_mux_determine_rate_flags(struct clk_hw *hw,
1317 struct clk_rate_request *req,
1318 unsigned long flags);
1319 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
1320 void clk_hw_get_rate_range(struct clk_hw *hw, unsigned long *min_rate,
1321 unsigned long *max_rate);
1322 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
1323 unsigned long max_rate);
1324
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)1325 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
1326 {
1327 dst->clk = src->clk;
1328 dst->core = src->core;
1329 }
1330
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)1331 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
1332 unsigned long *prate,
1333 const struct clk_div_table *table,
1334 u8 width, unsigned long flags)
1335 {
1336 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
1337 rate, prate, table, width, flags);
1338 }
1339
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)1340 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
1341 unsigned long *prate,
1342 const struct clk_div_table *table,
1343 u8 width, unsigned long flags,
1344 unsigned int val)
1345 {
1346 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
1347 rate, prate, table, width, flags,
1348 val);
1349 }
1350
1351 /*
1352 * FIXME clock api without lock protection
1353 */
1354 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
1355
1356 struct clk_onecell_data {
1357 struct clk **clks;
1358 unsigned int clk_num;
1359 };
1360
1361 struct clk_hw_onecell_data {
1362 unsigned int num;
1363 struct clk_hw *hws[];
1364 };
1365
1366 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
1367
1368 /*
1369 * Use this macro when you have a driver that requires two initialization
1370 * routines, one at of_clk_init(), and one at platform device probe
1371 */
1372 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
1373 static void __init name##_of_clk_init_driver(struct device_node *np) \
1374 { \
1375 of_node_clear_flag(np, OF_POPULATED); \
1376 fn(np); \
1377 } \
1378 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
1379
1380 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
1381 (&(struct clk_init_data) { \
1382 .flags = _flags, \
1383 .name = _name, \
1384 .parent_names = (const char *[]) { _parent }, \
1385 .num_parents = 1, \
1386 .ops = _ops, \
1387 })
1388
1389 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
1390 (&(struct clk_init_data) { \
1391 .flags = _flags, \
1392 .name = _name, \
1393 .parent_hws = (const struct clk_hw*[]) { _parent }, \
1394 .num_parents = 1, \
1395 .ops = _ops, \
1396 })
1397
1398 /*
1399 * This macro is intended for drivers to be able to share the otherwise
1400 * individual struct clk_hw[] compound literals created by the compiler
1401 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
1402 */
1403 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
1404 (&(struct clk_init_data) { \
1405 .flags = _flags, \
1406 .name = _name, \
1407 .parent_hws = _parent, \
1408 .num_parents = 1, \
1409 .ops = _ops, \
1410 })
1411
1412 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
1413 (&(struct clk_init_data) { \
1414 .flags = _flags, \
1415 .name = _name, \
1416 .parent_data = (const struct clk_parent_data[]) { \
1417 { .fw_name = _parent }, \
1418 }, \
1419 .num_parents = 1, \
1420 .ops = _ops, \
1421 })
1422
1423 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
1424 (&(struct clk_init_data) { \
1425 .flags = _flags, \
1426 .name = _name, \
1427 .parent_names = _parents, \
1428 .num_parents = ARRAY_SIZE(_parents), \
1429 .ops = _ops, \
1430 })
1431
1432 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
1433 (&(struct clk_init_data) { \
1434 .flags = _flags, \
1435 .name = _name, \
1436 .parent_hws = _parents, \
1437 .num_parents = ARRAY_SIZE(_parents), \
1438 .ops = _ops, \
1439 })
1440
1441 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
1442 (&(struct clk_init_data) { \
1443 .flags = _flags, \
1444 .name = _name, \
1445 .parent_data = _parents, \
1446 .num_parents = ARRAY_SIZE(_parents), \
1447 .ops = _ops, \
1448 })
1449
1450 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
1451 (&(struct clk_init_data) { \
1452 .flags = _flags, \
1453 .name = _name, \
1454 .parent_names = NULL, \
1455 .num_parents = 0, \
1456 .ops = _ops, \
1457 })
1458
1459 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
1460 _div, _mult, _flags) \
1461 struct clk_fixed_factor _struct = { \
1462 .div = _div, \
1463 .mult = _mult, \
1464 .hw.init = CLK_HW_INIT(_name, \
1465 _parent, \
1466 &clk_fixed_factor_ops, \
1467 _flags), \
1468 }
1469
1470 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
1471 _div, _mult, _flags) \
1472 struct clk_fixed_factor _struct = { \
1473 .div = _div, \
1474 .mult = _mult, \
1475 .hw.init = CLK_HW_INIT_HW(_name, \
1476 _parent, \
1477 &clk_fixed_factor_ops, \
1478 _flags), \
1479 }
1480
1481 /*
1482 * This macro allows the driver to reuse the _parent array for multiple
1483 * fixed factor clk declarations.
1484 */
1485 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1486 _div, _mult, _flags) \
1487 struct clk_fixed_factor _struct = { \
1488 .div = _div, \
1489 .mult = _mult, \
1490 .hw.init = CLK_HW_INIT_HWS(_name, \
1491 _parent, \
1492 &clk_fixed_factor_ops, \
1493 _flags), \
1494 }
1495
1496 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1497 _div, _mult, _flags) \
1498 struct clk_fixed_factor _struct = { \
1499 .div = _div, \
1500 .mult = _mult, \
1501 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1502 _parent, \
1503 &clk_fixed_factor_ops, \
1504 _flags), \
1505 }
1506
1507 #ifdef CONFIG_OF
1508 int of_clk_add_provider(struct device_node *np,
1509 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1510 void *data),
1511 void *data);
1512 int of_clk_add_hw_provider(struct device_node *np,
1513 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1514 void *data),
1515 void *data);
1516 int devm_of_clk_add_hw_provider(struct device *dev,
1517 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1518 void *data),
1519 void *data);
1520 void of_clk_del_provider(struct device_node *np);
1521
1522 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1523 void *data);
1524 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1525 void *data);
1526 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1527 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1528 void *data);
1529 int of_clk_parent_fill(struct device_node *np, const char **parents,
1530 unsigned int size);
1531 int of_clk_detect_critical(struct device_node *np, int index,
1532 unsigned long *flags);
1533
1534 #else /* !CONFIG_OF */
1535
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1536 static inline int of_clk_add_provider(struct device_node *np,
1537 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1538 void *data),
1539 void *data)
1540 {
1541 return 0;
1542 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1543 static inline int of_clk_add_hw_provider(struct device_node *np,
1544 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1545 void *data),
1546 void *data)
1547 {
1548 return 0;
1549 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1550 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1551 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1552 void *data),
1553 void *data)
1554 {
1555 return 0;
1556 }
of_clk_del_provider(struct device_node * np)1557 static inline void of_clk_del_provider(struct device_node *np) {}
1558
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1559 static inline struct clk *of_clk_src_simple_get(
1560 struct of_phandle_args *clkspec, void *data)
1561 {
1562 return ERR_PTR(-ENOENT);
1563 }
1564 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1565 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1566 {
1567 return ERR_PTR(-ENOENT);
1568 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1569 static inline struct clk *of_clk_src_onecell_get(
1570 struct of_phandle_args *clkspec, void *data)
1571 {
1572 return ERR_PTR(-ENOENT);
1573 }
1574 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1575 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1576 {
1577 return ERR_PTR(-ENOENT);
1578 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1579 static inline int of_clk_parent_fill(struct device_node *np,
1580 const char **parents, unsigned int size)
1581 {
1582 return 0;
1583 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1584 static inline int of_clk_detect_critical(struct device_node *np, int index,
1585 unsigned long *flags)
1586 {
1587 return 0;
1588 }
1589 #endif /* CONFIG_OF */
1590
1591 void clk_gate_restore_context(struct clk_hw *hw);
1592
1593 #endif /* CLK_PROVIDER_H */
1594