1config 64BIT
2	bool
3	default ARCH != "arm32"
4	help
5	  Say yes to build a 64-bit Xen
6	  Say no to build a 32-bit Xen
7
8config ARM_32
9	def_bool y
10	depends on !64BIT
11
12config ARM_64
13	def_bool y
14	depends on 64BIT
15	select HAS_GICV3
16
17config ARM
18	def_bool y
19	select HAS_ALTERNATIVE
20	select HAS_ARM_HDLCD
21	select HAS_DEVICE_TREE
22	select HAS_MEM_ACCESS
23	select HAS_PASSTHROUGH
24	select HAS_PDX
25	select VIDEO
26
27config ARCH_DEFCONFIG
28	string
29	default "arch/arm/configs/arm32_defconfig" if ARM_32
30	default "arch/arm/configs/arm64_defconfig" if ARM_64
31
32menu "Architecture Features"
33
34source "arch/Kconfig"
35
36config ACPI
37	bool
38	prompt "ACPI (Advanced Configuration and Power Interface) Support" if EXPERT = "y"
39	depends on ARM_64
40	---help---
41
42	  Advanced Configuration and Power Interface (ACPI) support for Xen is
43	  an alternative to device tree on ARM64.
44
45config HAS_GICV3
46	bool
47
48config HAS_ITS
49        bool
50        prompt "GICv3 ITS MSI controller support" if EXPERT = "y"
51        depends on HAS_GICV3
52
53config SBSA_VUART_CONSOLE
54	bool "Emulated SBSA UART console support"
55	default y
56	---help---
57	  Allows a guest to use SBSA Generic UART as a console. The
58	  SBSA Generic UART implements a subset of ARM PL011 UART.
59
60endmenu
61
62menu "ARM errata workaround via the alternative framework"
63	depends on HAS_ALTERNATIVE
64
65config ARM64_ERRATUM_827319
66	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
67	default y
68	depends on ARM_64
69	help
70	  This option adds an alternative code sequence to work around ARM
71	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
72	  master interface and an L2 cache.
73
74	  Under certain conditions this erratum can cause a clean line eviction
75	  to occur at the same time as another transaction to the same address
76	  on the AMBA 5 CHI interface, which can cause data corruption if the
77	  interconnect reorders the two transactions.
78
79	  The workaround promotes data cache clean instructions to
80	  data cache clean-and-invalidate.
81	  Please note that this does not necessarily enable the workaround,
82	  as it depends on the alternative framework, which will only patch
83	  the kernel if an affected CPU is detected.
84
85	  If unsure, say Y.
86
87config ARM64_ERRATUM_824069
88	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
89	default y
90	depends on ARM_64
91	help
92	  This option adds an alternative code sequence to work around ARM
93	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
94	  to a coherent interconnect.
95
96	  If a Cortex-A53 processor is executing a store or prefetch for
97	  write instruction at the same time as a processor in another
98	  cluster is executing a cache maintenance operation to the same
99	  address, then this erratum might cause a clean cache line to be
100	  incorrectly marked as dirty.
101
102	  The workaround promotes data cache clean instructions to
103	  data cache clean-and-invalidate.
104	  Please note that this option does not necessarily enable the
105	  workaround, as it depends on the alternative framework, which will
106	  only patch the kernel if an affected CPU is detected.
107
108	  If unsure, say Y.
109
110config ARM64_ERRATUM_819472
111	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
112	default y
113	depends on ARM_64
114	help
115	  This option adds an alternative code sequence to work around ARM
116	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
117	  present when it is connected to a coherent interconnect.
118
119	  If the processor is executing a load and store exclusive sequence at
120	  the same time as a processor in another cluster is executing a cache
121	  maintenance operation to the same address, then this erratum might
122	  cause data corruption.
123
124	  The workaround promotes data cache clean instructions to
125	  data cache clean-and-invalidate.
126	  Please note that this does not necessarily enable the workaround,
127	  as it depends on the alternative framework, which will only patch
128	  the kernel if an affected CPU is detected.
129
130	  If unsure, say Y.
131
132config ARM64_ERRATUM_832075
133	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
134	default y
135	depends on ARM_64
136	help
137	  This option adds an alternative code sequence to work around ARM
138	  erratum 832075 on Cortex-A57 parts up to r1p2.
139
140	  Affected Cortex-A57 parts might deadlock when exclusive load/store
141	  instructions to Write-Back memory are mixed with Device loads.
142
143	  The workaround is to promote device loads to use Load-Acquire
144	  semantics.
145	  Please note that this does not necessarily enable the workaround,
146	  as it depends on the alternative framework, which will only patch
147	  the kernel if an affected CPU is detected.
148
149	  If unsure, say Y.
150
151config ARM64_ERRATUM_834220
152	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
153	default y
154	depends on ARM_64
155	help
156	  This option adds an alternative code sequence to work around ARM
157	  erratum 834220 on Cortex-A57 parts up to r1p2.
158
159	  Affected Cortex-A57 parts might report a Stage 2 translation
160	  fault as the result of a Stage 1 fault for load crossing a
161	  page boundary when there is a permission or device memory
162	  alignment fault at Stage 1 and a translation fault at Stage 2.
163
164	  The workaround is to verify that the Stage 1 translation
165	  doesn't generate a fault before handling the Stage 2 fault.
166	  Please note that this does not necessarily enable the workaround,
167	  as it depends on the alternative framework, which will only patch
168	  the kernel if an affected CPU is detected.
169
170	  If unsure, say Y.
171
172endmenu
173
174source "common/Kconfig"
175
176source "drivers/Kconfig"
177