1# SPDX-License-Identifier: GPL-2.0-only
2menu "RAM/ROM/Flash chip drivers"
3	depends on MTD!=n
4
5config MTD_CFI
6	tristate "Detect flash chips by Common Flash Interface (CFI) probe"
7	select MTD_GEN_PROBE
8	select MTD_CFI_UTIL
9	help
10	  The Common Flash Interface specification was developed by Intel,
11	  AMD and other flash manufactures that provides a universal method
12	  for probing the capabilities of flash devices. If you wish to
13	  support any device that is CFI-compliant, you need to enable this
14	  option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
15	  for more information on CFI.
16
17config MTD_JEDECPROBE
18	tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
19	select MTD_GEN_PROBE
20	select MTD_CFI_UTIL
21	help
22	  This option enables JEDEC-style probing of flash chips which are not
23	  compatible with the Common Flash Interface, but will use the common
24	  CFI-targeted flash drivers for any chips which are identified which
25	  are in fact compatible in all but the probe method. This actually
26	  covers most AMD/Fujitsu-compatible chips and also non-CFI
27	  Intel chips.
28
29config MTD_GEN_PROBE
30	tristate
31
32config MTD_CFI_ADV_OPTIONS
33	bool "Flash chip driver advanced configuration options"
34	depends on MTD_GEN_PROBE
35	help
36	  If you need to specify a specific endianness for access to flash
37	  chips, or if you wish to reduce the size of the kernel by including
38	  support for only specific arrangements of flash chips, say 'Y'. This
39	  option does not directly affect the code, but will enable other
40	  configuration options which allow you to do so.
41
42	  If unsure, say 'N'.
43
44choice
45	prompt "Flash cmd/query data swapping"
46	depends on MTD_CFI_ADV_OPTIONS
47	default MTD_CFI_NOSWAP
48	help
49	  This option defines the way in which the CPU attempts to arrange
50	  data bits when writing the 'magic' commands to the chips. Saying
51	  'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
52	  enabled, means that the CPU will not do any swapping; the chips
53	  are expected to be wired to the CPU in 'host-endian' form.
54	  Specific arrangements are possible with the BIG_ENDIAN_BYTE and
55	  LITTLE_ENDIAN_BYTE, if the bytes are reversed.
56
57config MTD_CFI_NOSWAP
58	depends on !ARCH_IXP4XX || CPU_BIG_ENDIAN
59	bool "NO"
60
61config MTD_CFI_BE_BYTE_SWAP
62	bool "BIG_ENDIAN_BYTE"
63
64config MTD_CFI_LE_BYTE_SWAP
65	depends on !ARCH_IXP4XX
66	bool "LITTLE_ENDIAN_BYTE"
67
68endchoice
69
70config MTD_CFI_GEOMETRY
71	bool "Specific CFI Flash geometry selection"
72	depends on MTD_CFI_ADV_OPTIONS
73	select MTD_MAP_BANK_WIDTH_1 if  !(MTD_MAP_BANK_WIDTH_2 || \
74		 MTD_MAP_BANK_WIDTH_4  || MTD_MAP_BANK_WIDTH_8 || \
75		 MTD_MAP_BANK_WIDTH_16 || MTD_MAP_BANK_WIDTH_32)
76	select MTD_CFI_I1 if !(MTD_CFI_I2 || MTD_CFI_I4 || MTD_CFI_I8)
77	help
78	  This option does not affect the code directly, but will enable
79	  some other configuration options which would allow you to reduce
80	  the size of the kernel by including support for only certain
81	  arrangements of CFI chips. If unsure, say 'N' and all options
82	  which are supported by the current code will be enabled.
83
84config MTD_MAP_BANK_WIDTH_1
85	bool "Support  8-bit buswidth" if MTD_CFI_GEOMETRY
86	default y
87	help
88	  If you wish to support CFI devices on a physical bus which is
89	  8 bits wide, say 'Y'.
90
91config MTD_MAP_BANK_WIDTH_2
92	bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
93	default y
94	help
95	  If you wish to support CFI devices on a physical bus which is
96	  16 bits wide, say 'Y'.
97
98config MTD_MAP_BANK_WIDTH_4
99	bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
100	default y
101	help
102	  If you wish to support CFI devices on a physical bus which is
103	  32 bits wide, say 'Y'.
104
105config MTD_MAP_BANK_WIDTH_8
106	bool "Support 64-bit buswidth" if MTD_CFI_GEOMETRY
107	default n
108	help
109	  If you wish to support CFI devices on a physical bus which is
110	  64 bits wide, say 'Y'.
111
112config MTD_MAP_BANK_WIDTH_16
113	bool "Support 128-bit buswidth" if MTD_CFI_GEOMETRY
114	default n
115	help
116	  If you wish to support CFI devices on a physical bus which is
117	  128 bits wide, say 'Y'.
118
119config MTD_MAP_BANK_WIDTH_32
120	bool "Support 256-bit buswidth" if MTD_CFI_GEOMETRY
121	select MTD_COMPLEX_MAPPINGS if HAS_IOMEM
122	default n
123	help
124	  If you wish to support CFI devices on a physical bus which is
125	  256 bits wide, say 'Y'.
126
127config MTD_CFI_I1
128	bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
129	default y
130	help
131	  If your flash chips are not interleaved - i.e. you only have one
132	  flash chip addressed by each bus cycle, then say 'Y'.
133
134config MTD_CFI_I2
135	bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
136	default y
137	help
138	  If your flash chips are interleaved in pairs - i.e. you have two
139	  flash chips addressed by each bus cycle, then say 'Y'.
140
141config MTD_CFI_I4
142	bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
143	default n
144	help
145	  If your flash chips are interleaved in fours - i.e. you have four
146	  flash chips addressed by each bus cycle, then say 'Y'.
147
148config MTD_CFI_I8
149	bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
150	default n
151	help
152	  If your flash chips are interleaved in eights - i.e. you have eight
153	  flash chips addressed by each bus cycle, then say 'Y'.
154
155config MTD_OTP
156	bool "Protection Registers aka one-time programmable (OTP) bits"
157	depends on MTD_CFI_ADV_OPTIONS
158	default n
159	help
160	  This enables support for reading, writing and locking so called
161	  "Protection Registers" present on some flash chips.
162	  A subset of them are pre-programmed at the factory with a
163	  unique set of values. The rest is user-programmable.
164
165	  The user-programmable Protection Registers contain one-time
166	  programmable (OTP) bits; when programmed, register bits cannot be
167	  erased. Each Protection Register can be accessed multiple times to
168	  program individual bits, as long as the register remains unlocked.
169
170	  Each Protection Register has an associated Lock Register bit. When a
171	  Lock Register bit is programmed, the associated Protection Register
172	  can only be read; it can no longer be programmed. Additionally,
173	  because the Lock Register bits themselves are OTP, when programmed,
174	  Lock Register bits cannot be erased. Therefore, when a Protection
175	  Register is locked, it cannot be unlocked.
176
177	  This feature should therefore be used with extreme care. Any mistake
178	  in the programming of OTP bits will waste them.
179
180config MTD_CFI_INTELEXT
181	tristate "Support for CFI command set 0001 (Intel/Sharp chips)"
182	depends on MTD_GEN_PROBE
183	select MTD_CFI_UTIL
184	help
185	  The Common Flash Interface defines a number of different command
186	  sets which a CFI-compliant chip may claim to implement. This code
187	  provides support for command set 0001, used on Intel StrataFlash
188	  and other parts.
189
190config MTD_CFI_AMDSTD
191	tristate "Support for CFI command set 0002 (AMD/Fujitsu/Spansion chips)"
192	depends on MTD_GEN_PROBE
193	select MTD_CFI_UTIL
194	help
195	  The Common Flash Interface defines a number of different command
196	  sets which a CFI-compliant chip may claim to implement. This code
197	  provides support for command set 0002, used on chips including
198	  the AMD Am29LV320.
199
200config MTD_CFI_STAA
201	tristate "Support for CFI command set 0020 (ST (Advanced Architecture) chips)"
202	depends on MTD_GEN_PROBE
203	select MTD_CFI_UTIL
204	help
205	  The Common Flash Interface defines a number of different command
206	  sets which a CFI-compliant chip may claim to implement. This code
207	  provides support for command set 0020.
208
209config MTD_CFI_UTIL
210	tristate
211
212config MTD_RAM
213	tristate "Support for RAM chips in bus mapping"
214	help
215	  This option enables basic support for RAM chips accessed through
216	  a bus mapping driver.
217
218config MTD_ROM
219	tristate "Support for ROM chips in bus mapping"
220	help
221	  This option enables basic support for ROM chips accessed through
222	  a bus mapping driver.
223
224config MTD_ABSENT
225	tristate "Support for absent chips in bus mapping"
226	help
227	  This option enables support for a dummy probing driver used to
228	  allocated placeholder MTD devices on systems that have socketed
229	  or removable media.  Use of this driver as a fallback chip probe
230	  preserves the expected registration order of MTD device nodes on
231	  the system regardless of media presence.  Device nodes created
232	  with this driver will return -ENODEV upon access.
233
234config MTD_XIP
235	bool "XIP aware MTD support"
236	depends on !SMP && (MTD_CFI_INTELEXT || MTD_CFI_AMDSTD) && ARCH_MTD_XIP
237	default y if XIP_KERNEL
238	help
239	  This allows MTD support to work with flash memory which is also
240	  used for XIP purposes.  If you're not sure what this is all about
241	  then say N.
242
243endmenu
244