1 /*
2  * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
3  *
4  * SPDX-License-Identifier: GPL-2.0-only
5  */
6 
7 #pragma once
8 
9 #include <config.h>
10 #include <sel4/sel4_arch/constants.h>
11 
12 #define PAGE_BITS seL4_PageBits
13 
14 /* Control register fields */
15 #define CONTROL_M         0  /* MMU enable */
16 #define CONTROL_A         1  /* Alignment check enable */
17 #define CONTROL_C         2  /* Cacheability control, for data caching */
18 #define CONTROL_SA0       4  /* Stack Alignment Check Enable for EL0 */
19 #define CONTROL_SA        3  /* Stack Alignment Check for EL1 */
20 #define CONTROL_I         12 /* Instruction access Cacheability control */
21 #define CONTROL_E0E       24 /* Endianness of data accesses at EL0 */
22 #define CONTROL_EE        25 /* Endianness of data accesses at EL1 */
23 
24 #ifndef __ASSEMBLER__
25 
26 #include <arch/types.h>
27 
28 enum vm_page_size {
29     ARMSmallPage,
30     ARMLargePage,
31     ARMHugePage
32 };
33 typedef word_t vm_page_size_t;
34 
35 enum frameSizeConstants {
36     ARMSmallPageBits    = seL4_PageBits,
37     ARMLargePageBits    = seL4_LargePageBits,
38     ARMHugePageBits     = seL4_HugePageBits
39 };
40 
pageBitsForSize(vm_page_size_t pagesize)41 static inline word_t CONST pageBitsForSize(vm_page_size_t pagesize)
42 {
43     switch (pagesize) {
44     case ARMSmallPage:
45         return ARMSmallPageBits;
46 
47     case ARMLargePage:
48         return ARMLargePageBits;
49 
50     case ARMHugePage:
51         return ARMHugePageBits;
52 
53     default:
54         fail("Invalid page size");
55     }
56 }
57 
58 #endif /* __ASSEMBLER__ */
59 
60