1 /*
2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A32_H
8 #define CORTEX_A32_H
9 
10 #include <lib/utils_def.h>
11 
12 /* Cortex-A32 Main ID register for revision 0 */
13 #define CORTEX_A32_MIDR				U(0x410FD010)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions.
17  * CPUECTLR_EL1 is an implementation-specific register.
18  ******************************************************************************/
19 #define CORTEX_A32_CPUECTLR_EL1			p15, 1, c15
20 #define CORTEX_A32_CPUECTLR_SMPEN_BIT		(ULL(1) << 6)
21 
22 #endif /* CORTEX_A32_H */
23