1 /*
2 * Copyright (c) 2008-2013 Travis Geiselbrecht
3 *
4 * Use of this source code is governed by a MIT-style
5 * license that can be found in the LICENSE file or at
6 * https://opensource.org/licenses/MIT
7 */
8 #ifndef __ARCH_ARM_H
9 #define __ARCH_ARM_H
10
11 #include <stdbool.h>
12 #include <sys/types.h>
13 #include <arch/arm/cores.h>
14 #include <lk/compiler.h>
15
16 /* due to the cp15 accessors below, you're gonna have a bad time if you try
17 * to compile in thumb mode. Either compile in ARM only or get a thumb2 capable cpu.
18
19 #if defined(__thumb__) && !defined(__thumb2__)
20 #error this file unsupported in thumb1 mode
21 #endif
22 */
23 __BEGIN_CDECLS
24
25 #if ARM_ISA_ARMV7
26 #define DSB __asm__ volatile("dsb" ::: "memory")
27 #define DMB __asm__ volatile("dmb" ::: "memory")
28 #define ISB __asm__ volatile("isb" ::: "memory")
29 #elif ARM_ISA_ARMV6 || ARM_ISA_ARMV6M
30 #define DSB __asm__ volatile("mcr p15, 0, %0, c7, c10, 4" :: "r" (0) : "memory")
31 #define ISB __asm__ volatile("mcr p15, 0, %0, c7, c5, 4" :: "r" (0) : "memory")
32 #define DMB __asm__ volatile("nop")
33 #else
34 #error unhandled arm isa
35 #endif
36 #define NOP __asm__ volatile("nop");
37
38 void arm_context_switch(vaddr_t *old_sp, vaddr_t new_sp);
39
40 void arm_chain_load(paddr_t entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) __NO_RETURN;
41
read_cpsr(void)42 static inline uint32_t read_cpsr(void) {
43 uint32_t cpsr;
44
45 __asm__ volatile("mrs %0, cpsr" : "=r" (cpsr));
46 return cpsr;
47 }
48
49 #define CPSR_MODE_MASK 0x1f
50 #define CPSR_MODE_USR 0x10
51 #define CPSR_MODE_FIQ 0x11
52 #define CPSR_MODE_IRQ 0x12
53 #define CPSR_MODE_SVC 0x13
54 #define CPSR_MODE_MON 0x16
55 #define CPSR_MODE_ABT 0x17
56 #define CPSR_MODE_UND 0x1b
57 #define CPSR_MODE_SYS 0x1f
58 #define CPSR_THUMB (1<<5)
59 #define CPSR_FIQ_MASK (1<<6)
60 #define CPSR_IRQ_MASK (1<<7)
61 #define CPSR_ABORT (1<<8)
62 #define CPSR_ENDIAN (1<<9)
63
64 struct arm_iframe {
65 #if ARM_WITH_VFP
66 uint32_t fpexc;
67 #endif
68 uint32_t usp;
69 uint32_t ulr;
70 uint32_t r0;
71 uint32_t r1;
72 uint32_t r2;
73 uint32_t r3;
74 uint32_t r12;
75 uint32_t lr;
76 uint32_t pc;
77 uint32_t spsr;
78 };
79
80 struct arm_fault_frame {
81 #if ARM_WITH_VFP
82 uint32_t fpexc;
83 #endif
84 uint32_t usp;
85 uint32_t ulr;
86 uint32_t r[13];
87 uint32_t lr;
88 uint32_t pc;
89 uint32_t spsr;
90 };
91
92 struct arm_mode_regs {
93 uint32_t usr_r13, usr_r14;
94 uint32_t fiq_r13, fiq_r14;
95 uint32_t irq_r13, irq_r14;
96 uint32_t svc_r13, svc_r14;
97 uint32_t abt_r13, abt_r14;
98 uint32_t und_r13, und_r14;
99 uint32_t sys_r13, sys_r14;
100 };
101
102 void arm_save_mode_regs(struct arm_mode_regs *regs);
103
104 #define GEN_CP_REG_FUNCS(cp, reg, op1, c1, c2, op2) \
105 static inline __ALWAYS_INLINE uint32_t arm_read_##reg(void) { \
106 uint32_t val; \
107 __asm__ volatile("mrc " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 : "=r" (val)); \
108 return val; \
109 } \
110 \
111 static inline __ALWAYS_INLINE uint32_t arm_read_##reg##_relaxed(void) { \
112 uint32_t val; \
113 __asm__("mrc " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 : "=r" (val)); \
114 return val; \
115 } \
116 \
117 static inline __ALWAYS_INLINE void arm_write_##reg(uint32_t val) { \
118 __asm__ volatile("mcr " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 :: "r" (val)); \
119 ISB; \
120 } \
121 \
122 static inline __ALWAYS_INLINE void arm_write_##reg##_relaxed(uint32_t val) { \
123 __asm__ volatile("mcr " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 :: "r" (val)); \
124 }
125
126 #define GEN_CP15_REG_FUNCS(reg, op1, c1, c2, op2) \
127 GEN_CP_REG_FUNCS(p15, reg, op1, c1, c2, op2)
128
129 #define GEN_CP14_REG_FUNCS(reg, op1, c1, c2, op2) \
130 GEN_CP_REG_FUNCS(p14, reg, op1, c1, c2, op2)
131
132 /* armv6+ control regs */
133 GEN_CP15_REG_FUNCS(sctlr, 0, c1, c0, 0);
134 GEN_CP15_REG_FUNCS(actlr, 0, c1, c0, 1);
135 GEN_CP15_REG_FUNCS(cpacr, 0, c1, c0, 2);
136
137 GEN_CP15_REG_FUNCS(ttbr, 0, c2, c0, 0);
138 GEN_CP15_REG_FUNCS(ttbr0, 0, c2, c0, 0);
139 GEN_CP15_REG_FUNCS(ttbr1, 0, c2, c0, 1);
140 GEN_CP15_REG_FUNCS(ttbcr, 0, c2, c0, 2);
141 GEN_CP15_REG_FUNCS(dacr, 0, c3, c0, 0);
142 GEN_CP15_REG_FUNCS(dfsr, 0, c5, c0, 0);
143 GEN_CP15_REG_FUNCS(ifsr, 0, c5, c0, 1);
144 GEN_CP15_REG_FUNCS(dfar, 0, c6, c0, 0);
145 GEN_CP15_REG_FUNCS(wfar, 0, c6, c0, 1);
146 GEN_CP15_REG_FUNCS(ifar, 0, c6, c0, 2);
147
148 GEN_CP15_REG_FUNCS(fcseidr, 0, c13, c0, 0);
149 GEN_CP15_REG_FUNCS(contextidr, 0, c13, c0, 1);
150 GEN_CP15_REG_FUNCS(tpidrurw, 0, c13, c0, 2);
151 GEN_CP15_REG_FUNCS(tpidruro, 0, c13, c0, 3);
152 GEN_CP15_REG_FUNCS(tpidrprw, 0, c13, c0, 4);
153
154 /* armv7+ */
155 GEN_CP15_REG_FUNCS(midr, 0, c0, c0, 0);
156 GEN_CP15_REG_FUNCS(mpidr, 0, c0, c0, 5);
157 GEN_CP15_REG_FUNCS(vbar, 0, c12, c0, 0);
158 GEN_CP15_REG_FUNCS(cbar, 4, c15, c0, 0);
159
160 GEN_CP15_REG_FUNCS(ats1cpr, 0, c7, c8, 0);
161 GEN_CP15_REG_FUNCS(ats1cpw, 0, c7, c8, 1);
162 GEN_CP15_REG_FUNCS(ats1cur, 0, c7, c8, 2);
163 GEN_CP15_REG_FUNCS(ats1cuw, 0, c7, c8, 3);
164 GEN_CP15_REG_FUNCS(ats12nsopr, 0, c7, c8, 4);
165 GEN_CP15_REG_FUNCS(ats12nsopw, 0, c7, c8, 5);
166 GEN_CP15_REG_FUNCS(ats12nsour, 0, c7, c8, 6);
167 GEN_CP15_REG_FUNCS(ats12nsouw, 0, c7, c8, 7);
168 GEN_CP15_REG_FUNCS(par, 0, c7, c4, 0);
169
170 /* Branch predictor invalidate */
171 GEN_CP15_REG_FUNCS(bpiall, 0, c7, c5, 6);
172 GEN_CP15_REG_FUNCS(bpimva, 0, c7, c5, 7);
173 GEN_CP15_REG_FUNCS(bpiallis, 0, c7, c1, 6);
174
175 /* tlb registers */
176 GEN_CP15_REG_FUNCS(tlbiallis, 0, c8, c3, 0);
177 GEN_CP15_REG_FUNCS(tlbimvais, 0, c8, c3, 1);
178 GEN_CP15_REG_FUNCS(tlbiasidis, 0, c8, c3, 2);
179 GEN_CP15_REG_FUNCS(tlbimvaais, 0, c8, c3, 3);
180 GEN_CP15_REG_FUNCS(itlbiall, 0, c8, c5, 0);
181 GEN_CP15_REG_FUNCS(itlbimva, 0, c8, c5, 1);
182 GEN_CP15_REG_FUNCS(itlbiasid, 0, c8, c5, 2);
183 GEN_CP15_REG_FUNCS(dtlbiall, 0, c8, c6, 0);
184 GEN_CP15_REG_FUNCS(dtlbimva, 0, c8, c6, 1);
185 GEN_CP15_REG_FUNCS(dtlbiasid, 0, c8, c6, 2);
186 GEN_CP15_REG_FUNCS(tlbiall, 0, c8, c7, 0);
187 GEN_CP15_REG_FUNCS(tlbimva, 0, c8, c7, 1);
188 GEN_CP15_REG_FUNCS(tlbiasid, 0, c8, c7, 2);
189 GEN_CP15_REG_FUNCS(tlbimvaa, 0, c8, c7, 3);
190
191 GEN_CP15_REG_FUNCS(l2ctlr, 1, c9, c0, 2);
192 GEN_CP15_REG_FUNCS(l2ectlr, 1, c9, c0, 3);
193
194 /* debug registers */
195 GEN_CP14_REG_FUNCS(dbddidr, 0, c0, c0, 0);
196 GEN_CP14_REG_FUNCS(dbgdrar, 0, c1, c0, 0);
197 GEN_CP14_REG_FUNCS(dbgdsar, 0, c2, c0, 0);
198 GEN_CP14_REG_FUNCS(dbgdscr, 0, c0, c1, 0);
199 GEN_CP14_REG_FUNCS(dbgdtrtxint, 0, c0, c5, 0);
200 GEN_CP14_REG_FUNCS(dbgdtrrxint, 0, c0, c5, 0); /* alias to previous */
201 GEN_CP14_REG_FUNCS(dbgwfar, 0, c0, c6, 0);
202 GEN_CP14_REG_FUNCS(dbgvcr, 0, c0, c7, 0);
203 GEN_CP14_REG_FUNCS(dbgecr, 0, c0, c9, 0);
204 GEN_CP14_REG_FUNCS(dbgdsccr, 0, c0, c10, 0);
205 GEN_CP14_REG_FUNCS(dbgdsmcr, 0, c0, c11, 0);
206 GEN_CP14_REG_FUNCS(dbgdtrrxext, 0, c0, c0, 2);
207 GEN_CP14_REG_FUNCS(dbgdscrext, 0, c0, c2, 2);
208 GEN_CP14_REG_FUNCS(dbgdtrtxext, 0, c0, c3, 2);
209 GEN_CP14_REG_FUNCS(dbgdrcr, 0, c0, c4, 2);
210 GEN_CP14_REG_FUNCS(dbgvr0, 0, c0, c0, 4);
211 GEN_CP14_REG_FUNCS(dbgvr1, 0, c0, c1, 4);
212 GEN_CP14_REG_FUNCS(dbgvr2, 0, c0, c2, 4);
213 GEN_CP14_REG_FUNCS(dbgbcr0, 0, c0, c0, 5);
214 GEN_CP14_REG_FUNCS(dbgbcr1, 0, c0, c1, 5);
215 GEN_CP14_REG_FUNCS(dbgbcr2, 0, c0, c2, 5);
216 GEN_CP14_REG_FUNCS(dbgwvr0, 0, c0, c0, 6);
217 GEN_CP14_REG_FUNCS(dbgwvr1, 0, c0, c1, 6);
218 GEN_CP14_REG_FUNCS(dbgwcr0, 0, c0, c0, 7);
219 GEN_CP14_REG_FUNCS(dbgwcr1, 0, c0, c1, 7);
220 GEN_CP14_REG_FUNCS(dbgoslar, 0, c1, c0, 4);
221 GEN_CP14_REG_FUNCS(dbgoslsr, 0, c1, c1, 4);
222 GEN_CP14_REG_FUNCS(dbgossrr, 0, c1, c2, 4);
223 GEN_CP14_REG_FUNCS(dbgprcr, 0, c1, c4, 4);
224 GEN_CP14_REG_FUNCS(dbgprsr, 0, c1, c5, 4);
225 GEN_CP14_REG_FUNCS(dbgclaimset, 0, c7, c8, 6);
226 GEN_CP14_REG_FUNCS(dbgclaimclr, 0, c7, c9, 6);
227 GEN_CP14_REG_FUNCS(dbgauthstatus, 0, c7, c14, 6);
228 GEN_CP14_REG_FUNCS(dbgdevid, 0, c7, c2, 7);
229
230 /* fpu */
231 void arm_fpu_set_enable(bool enable);
232 #if ARM_WITH_VFP
233 void arm_fpu_undefined_instruction(struct arm_iframe *frame);
234 struct thread;
235 void arm_fpu_thread_initialize(struct thread *t);
236 void arm_fpu_thread_swap(struct thread *oldthread, struct thread *newthread);
237 #endif
238
239 __END_CDECLS
240
241 #endif
242