1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2016, Xilinx Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef PLATFORM_CONFIG_H 30 #define PLATFORM_CONFIG_H 31 32 #include <mm/generic_ram_layout.h> 33 34 /* Make stacks aligned to data cache line length */ 35 #define CACHELINE_LEN 64 36 #define STACK_ALIGNMENT CACHELINE_LEN 37 38 #ifdef CFG_WITH_PAGER 39 #error "Pager not supported for zynqmp" 40 #endif 41 42 /* DDR Low area base */ 43 #define DRAM0_BASE 0 44 45 #ifdef ARM64 46 /* DDR High area base is only available when compiling for 64 bits */ 47 #define DRAM1_BASE 0x800000000 48 #endif 49 50 #ifdef CFG_CDNS_UART 51 #define CONSOLE_UART_BASE (CFG_UART_BASE) 52 #define IT_CONSOLE_UART (CFG_UART_IT) 53 #define CONSOLE_UART_CLK_IN_HZ (CFG_UART_CLK_HZ) 54 #endif 55 56 #if defined(PLATFORM_FLAVOR_zc1751_dc1) || \ 57 defined(PLATFORM_FLAVOR_zc1751_dc2) || \ 58 defined(PLATFORM_FLAVOR_zcu102) || \ 59 defined(PLATFORM_FLAVOR_zcu104) || \ 60 defined(PLATFORM_FLAVOR_zcu106) 61 62 #define GIC_BASE 0xF9010000 63 #define UART0_BASE 0xFF000000 64 #define UART1_BASE 0xFF010000 65 66 #define IT_UART0 53 67 #define IT_UART1 54 68 69 #define UART0_CLK_IN_HZ 100000000 70 #define UART1_CLK_IN_HZ 100000000 71 72 #define GICD_OFFSET 0 73 #define GICC_OFFSET 0x20000 74 75 #elif defined(PLATFORM_FLAVOR_ultra96) 76 77 #define GIC_BASE 0xF9010000 78 #define UART0_BASE 0xFF000000 79 #define UART1_BASE 0xFF010000 80 81 #define IT_UART0 53 82 #define IT_UART1 54 83 84 #define UART0_CLK_IN_HZ 100000000 85 #define UART1_CLK_IN_HZ 100000000 86 87 #define GICD_OFFSET 0 88 #define GICC_OFFSET 0x20000 89 90 #else 91 #error "Unknown platform flavor" 92 #endif 93 94 #define CSUDMA_BASE 0xFFC80000 95 #define CSUDMA_SIZE 0x1000 96 #define CSU_BASE 0xFFCA0000 97 #define CSU_SIZE 0x5038 98 99 #ifdef CFG_TEE_LOAD_ADDR 100 #define TEE_LOAD_ADDR CFG_TEE_LOAD_ADDR 101 #else 102 #define TEE_LOAD_ADDR TEE_RAM_START 103 #endif 104 105 #ifndef UART_BAUDRATE 106 #define UART_BAUDRATE 115200 107 #endif 108 #ifndef CONSOLE_BAUDRATE 109 #define CONSOLE_BAUDRATE UART_BAUDRATE 110 #endif 111 112 /* For virtual platforms where there isn't a clock */ 113 #ifndef CONSOLE_UART_CLK_IN_HZ 114 #define CONSOLE_UART_CLK_IN_HZ 1 115 #endif 116 117 #endif /*PLATFORM_CONFIG_H*/ 118