1 /* 2 * Copyright (c) 2020-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_NOC_H 8 #define SOCFPGA_NOC_H 9 10 /* Macros */ 11 #define SCR_AXI_AP_MASK BIT(24) 12 #define SCR_FPGA2SOC_MASK BIT(16) 13 #define SCR_MPU_MASK BIT(0) 14 #define DISABLE_L4_FIREWALL (SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \ 15 | SCR_MPU_MASK) 16 #define DISABLE_BRIDGE_FIREWALL 0x0ffe0101 17 18 #define SOCFPGA_CCU_NOC(_ctrl, _dev) (SOCFPGA_CCU_NOC_REG_BASE \ 19 + (SOCFPGA_CCU_NOC_##_ctrl##_##_dev)) 20 21 #define SOCFPGA_L4_PER_SCR(_reg) (SOCFPGA_L4_PER_SCR_REG_BASE \ 22 + (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg)) 23 24 #define SOCFPGA_L4_SYS_SCR(_reg) (SOCFPGA_L4_SYS_SCR_REG_BASE \ 25 + (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg)) 26 27 /* L3 Interconnect Register Map */ 28 #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER 0x0000 29 #define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA 0x0004 30 #define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER 0x000c 31 #define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER 0x0010 32 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0 0x001c 33 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1 0x0020 34 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0x0024 35 #define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0x0028 36 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0 0x002c 37 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1 0x0030 38 #define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2 0x0034 39 #define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC 0x0040 40 #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0 0x0044 41 #define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1 0x0048 42 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0 0x0050 43 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1 0x0054 44 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2 0x0058 45 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3 0x005c 46 #define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4 0x0060 47 #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0 0x0064 48 #define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1 0x0068 49 #define SOCFPGA_NOC_FW_L4_PER_SCR_UART0 0x006c 50 #define SOCFPGA_NOC_FW_L4_PER_SCR_UART1 0x0070 51 52 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC 0x0008 53 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0x000c 54 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0x0010 55 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0x0014 56 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0x0018 57 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0x001c 58 #define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0x0020 59 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC 0x002c 60 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0x0030 61 #define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0x0034 62 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0x0038 63 #define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0x0040 64 #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC 0x0044 65 #define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC 0x0048 66 #define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR 0x004c 67 #define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR 0x0054 68 #define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR 0x0058 69 #define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR 0x005c 70 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0x0060 71 #define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0x0064 72 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0 0x0068 73 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1 0x006c 74 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2 0x0070 75 #define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3 0x0074 76 #define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP 0x0078 77 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0x0090 78 #define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0x0094 79 80 /* CCU NOC Register Map */ 81 82 #define SOCFPGA_CCU_NOC_CPU0_RAM0 0x04688 83 #define SOCFPGA_CCU_NOC_IOM_RAM0 0x18628 84 85 #define SOCFPGA_CCU_NOC_ADMASK_P_MASK BIT(0) 86 #define SOCFPGA_CCU_NOC_ADMASK_NS_MASK BIT(1) 87 88 /* Function Definitions */ 89 90 void enable_ns_peripheral_access(void); 91 void enable_ns_bridge_access(void); 92 void enable_ns_ocram_access(void); 93 void enable_ocram_firewall(void); 94 95 #endif 96