1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef __INTEL_DMC_H__
7 #define __INTEL_DMC_H__
8 
9 #include "i915_reg_defs.h"
10 #include "intel_wakeref.h"
11 #include <linux/workqueue.h>
12 
13 struct drm_i915_error_state_buf;
14 struct drm_i915_private;
15 
16 enum pipe;
17 
18 enum {
19 	DMC_FW_MAIN = 0,
20 	DMC_FW_PIPEA,
21 	DMC_FW_PIPEB,
22 	DMC_FW_PIPEC,
23 	DMC_FW_PIPED,
24 	DMC_FW_MAX
25 };
26 
27 struct intel_dmc {
28 	struct work_struct work;
29 	const char *fw_path;
30 	u32 max_fw_size; /* bytes */
31 	u32 version;
32 	struct dmc_fw_info {
33 		u32 mmio_count;
34 		i915_reg_t mmioaddr[20];
35 		u32 mmiodata[20];
36 		u32 dmc_offset;
37 		u32 start_mmioaddr;
38 		u32 dmc_fw_size; /*dwords */
39 		u32 *payload;
40 		bool present;
41 	} dmc_info[DMC_FW_MAX];
42 
43 	u32 dc_state;
44 	u32 target_dc_state;
45 	u32 allowed_dc_mask;
46 	intel_wakeref_t wakeref;
47 };
48 
49 void intel_dmc_ucode_init(struct drm_i915_private *i915);
50 void intel_dmc_load_program(struct drm_i915_private *i915);
51 void intel_dmc_disable_program(struct drm_i915_private *i915);
52 void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe);
53 void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe);
54 void intel_dmc_ucode_fini(struct drm_i915_private *i915);
55 void intel_dmc_ucode_suspend(struct drm_i915_private *i915);
56 void intel_dmc_ucode_resume(struct drm_i915_private *i915);
57 bool intel_dmc_has_payload(struct drm_i915_private *i915);
58 void intel_dmc_debugfs_register(struct drm_i915_private *i915);
59 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
60 				 struct drm_i915_private *i915);
61 
62 void assert_dmc_loaded(struct drm_i915_private *i915);
63 
64 #endif /* __INTEL_DMC_H__ */
65