1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/V2M Pin Control and GPIO driver core
4 *
5 * Based on:
6 * Renesas RZ/G2L Pin Control and GPIO driver core
7 *
8 * Copyright (C) 2022 Renesas Electronics Corporation.
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/gpio/driver.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/spinlock.h>
19
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/pinctrl.h>
24 #include <linux/pinctrl/pinmux.h>
25
26 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
27
28 #include "../core.h"
29 #include "../pinconf.h"
30 #include "../pinmux.h"
31
32 #define DRV_NAME "pinctrl-rzv2m"
33
34 /*
35 * Use 16 lower bits [15:0] for pin identifier
36 * Use 16 higher bits [31:16] for pin mux function
37 */
38 #define MUX_PIN_ID_MASK GENMASK(15, 0)
39 #define MUX_FUNC_MASK GENMASK(31, 16)
40 #define MUX_FUNC(pinconf) FIELD_GET(MUX_FUNC_MASK, (pinconf))
41
42 /* PIN capabilities */
43 #define PIN_CFG_GRP_1_8V_2 1
44 #define PIN_CFG_GRP_1_8V_3 2
45 #define PIN_CFG_GRP_SWIO_1 3
46 #define PIN_CFG_GRP_SWIO_2 4
47 #define PIN_CFG_GRP_3_3V 5
48 #define PIN_CFG_GRP_MASK GENMASK(2, 0)
49 #define PIN_CFG_BIAS BIT(3)
50 #define PIN_CFG_DRV BIT(4)
51 #define PIN_CFG_SLEW BIT(5)
52
53 #define RZV2M_MPXED_PIN_FUNCS (PIN_CFG_BIAS | \
54 PIN_CFG_DRV | \
55 PIN_CFG_SLEW)
56
57 /*
58 * n indicates number of pins in the port, a is the register index
59 * and f is pin configuration capabilities supported.
60 */
61 #define RZV2M_GPIO_PORT_PACK(n, a, f) (((n) << 24) | ((a) << 16) | (f))
62 #define RZV2M_GPIO_PORT_GET_PINCNT(x) FIELD_GET(GENMASK(31, 24), (x))
63 #define RZV2M_GPIO_PORT_GET_INDEX(x) FIELD_GET(GENMASK(23, 16), (x))
64 #define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
65
66 #define RZV2M_DEDICATED_PORT_IDX 22
67
68 /*
69 * BIT(31) indicates dedicated pin, b is the register bits (b * 16)
70 * and f is the pin configuration capabilities supported.
71 */
72 #define RZV2M_SINGLE_PIN BIT(31)
73 #define RZV2M_SINGLE_PIN_PACK(b, f) (RZV2M_SINGLE_PIN | \
74 ((RZV2M_DEDICATED_PORT_IDX) << 24) | \
75 ((b) << 16) | (f))
76 #define RZV2M_SINGLE_PIN_GET_PORT(x) FIELD_GET(GENMASK(30, 24), (x))
77 #define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x))
78 #define RZV2M_SINGLE_PIN_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
79
80 #define RZV2M_PIN_ID_TO_PORT(id) ((id) / RZV2M_PINS_PER_PORT)
81 #define RZV2M_PIN_ID_TO_PIN(id) ((id) % RZV2M_PINS_PER_PORT)
82
83 #define DO(n) (0x00 + (n) * 0x40)
84 #define OE(n) (0x04 + (n) * 0x40)
85 #define IE(n) (0x08 + (n) * 0x40)
86 #define PFSEL(n) (0x10 + (n) * 0x40)
87 #define DI(n) (0x20 + (n) * 0x40)
88 #define PUPD(n) (0x24 + (n) * 0x40)
89 #define DRV(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \
90 : 0x590)
91 #define SR(n) ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \
92 : 0x594)
93 #define DI_MSK(n) (0x30 + (n) * 0x40)
94 #define EN_MSK(n) (0x34 + (n) * 0x40)
95
96 #define PFC_MASK 0x07
97 #define PUPD_MASK 0x03
98 #define DRV_MASK 0x03
99
100 struct rzv2m_dedicated_configs {
101 const char *name;
102 u32 config;
103 };
104
105 struct rzv2m_pinctrl_data {
106 const char * const *port_pins;
107 const u32 *port_pin_configs;
108 const struct rzv2m_dedicated_configs *dedicated_pins;
109 unsigned int n_port_pins;
110 unsigned int n_dedicated_pins;
111 };
112
113 struct rzv2m_pinctrl {
114 struct pinctrl_dev *pctl;
115 struct pinctrl_desc desc;
116 struct pinctrl_pin_desc *pins;
117
118 const struct rzv2m_pinctrl_data *data;
119 void __iomem *base;
120 struct device *dev;
121 struct clk *clk;
122
123 struct gpio_chip gpio_chip;
124 struct pinctrl_gpio_range gpio_range;
125
126 spinlock_t lock;
127 };
128
129 static const unsigned int drv_1_8V_group2_uA[] = { 1800, 3800, 7800, 11000 };
130 static const unsigned int drv_1_8V_group3_uA[] = { 1600, 3200, 6400, 9600 };
131 static const unsigned int drv_SWIO_group2_3_3V_uA[] = { 9000, 11000, 13000, 18000 };
132 static const unsigned int drv_3_3V_group_uA[] = { 2000, 4000, 8000, 12000 };
133
134 /* Helper for registers that have a write enable bit in the upper word */
rzv2m_writel_we(void __iomem * addr,u8 shift,u8 value)135 static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value)
136 {
137 writel((BIT(16) | value) << shift, addr);
138 }
139
rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl * pctrl,u8 port,u8 pin,u8 func)140 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl,
141 u8 port, u8 pin, u8 func)
142 {
143 void __iomem *addr;
144
145 /* Mask input/output */
146 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1);
147 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1);
148
149 /* Select the function and set the write enable bits */
150 addr = pctrl->base + PFSEL(port) + (pin / 4) * 4;
151 writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr);
152
153 /* Unmask input/output */
154 rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0);
155 rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0);
156 };
157
rzv2m_pinctrl_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)158 static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev,
159 unsigned int func_selector,
160 unsigned int group_selector)
161 {
162 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
163 struct function_desc *func;
164 unsigned int i, *psel_val;
165 struct group_desc *group;
166 int *pins;
167
168 func = pinmux_generic_get_function(pctldev, func_selector);
169 if (!func)
170 return -EINVAL;
171 group = pinctrl_generic_get_group(pctldev, group_selector);
172 if (!group)
173 return -EINVAL;
174
175 psel_val = func->data;
176 pins = group->pins;
177
178 for (i = 0; i < group->num_pins; i++) {
179 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
180 RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]),
181 psel_val[i]);
182 rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]),
183 RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
184 }
185
186 return 0;
187 };
188
rzv2m_map_add_config(struct pinctrl_map * map,const char * group_or_pin,enum pinctrl_map_type type,unsigned long * configs,unsigned int num_configs)189 static int rzv2m_map_add_config(struct pinctrl_map *map,
190 const char *group_or_pin,
191 enum pinctrl_map_type type,
192 unsigned long *configs,
193 unsigned int num_configs)
194 {
195 unsigned long *cfgs;
196
197 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
198 GFP_KERNEL);
199 if (!cfgs)
200 return -ENOMEM;
201
202 map->type = type;
203 map->data.configs.group_or_pin = group_or_pin;
204 map->data.configs.configs = cfgs;
205 map->data.configs.num_configs = num_configs;
206
207 return 0;
208 }
209
rzv2m_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps,unsigned int * index)210 static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
211 struct device_node *np,
212 struct pinctrl_map **map,
213 unsigned int *num_maps,
214 unsigned int *index)
215 {
216 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
217 struct pinctrl_map *maps = *map;
218 unsigned int nmaps = *num_maps;
219 unsigned long *configs = NULL;
220 unsigned int *pins, *psel_val;
221 unsigned int num_pinmux = 0;
222 unsigned int idx = *index;
223 unsigned int num_pins, i;
224 unsigned int num_configs;
225 struct property *pinmux;
226 struct property *prop;
227 int ret, gsel, fsel;
228 const char **pin_fn;
229 const char *pin;
230
231 pinmux = of_find_property(np, "pinmux", NULL);
232 if (pinmux)
233 num_pinmux = pinmux->length / sizeof(u32);
234
235 ret = of_property_count_strings(np, "pins");
236 if (ret == -EINVAL) {
237 num_pins = 0;
238 } else if (ret < 0) {
239 dev_err(pctrl->dev, "Invalid pins list in DT\n");
240 return ret;
241 } else {
242 num_pins = ret;
243 }
244
245 if (!num_pinmux && !num_pins)
246 return 0;
247
248 if (num_pinmux && num_pins) {
249 dev_err(pctrl->dev,
250 "DT node must contain either a pinmux or pins and not both\n");
251 return -EINVAL;
252 }
253
254 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
255 if (ret < 0)
256 return ret;
257
258 if (num_pins && !num_configs) {
259 dev_err(pctrl->dev, "DT node must contain a config\n");
260 ret = -ENODEV;
261 goto done;
262 }
263
264 if (num_pinmux)
265 nmaps += 1;
266
267 if (num_pins)
268 nmaps += num_pins;
269
270 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
271 if (!maps) {
272 ret = -ENOMEM;
273 goto done;
274 }
275
276 *map = maps;
277 *num_maps = nmaps;
278 if (num_pins) {
279 of_property_for_each_string(np, "pins", prop, pin) {
280 ret = rzv2m_map_add_config(&maps[idx], pin,
281 PIN_MAP_TYPE_CONFIGS_PIN,
282 configs, num_configs);
283 if (ret < 0)
284 goto done;
285
286 idx++;
287 }
288 ret = 0;
289 goto done;
290 }
291
292 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
293 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
294 GFP_KERNEL);
295 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
296 if (!pins || !psel_val || !pin_fn) {
297 ret = -ENOMEM;
298 goto done;
299 }
300
301 /* Collect pin locations and mux settings from DT properties */
302 for (i = 0; i < num_pinmux; ++i) {
303 u32 value;
304
305 ret = of_property_read_u32_index(np, "pinmux", i, &value);
306 if (ret)
307 goto done;
308 pins[i] = value & MUX_PIN_ID_MASK;
309 psel_val[i] = MUX_FUNC(value);
310 }
311
312 /* Register a single pin group listing all the pins we read from DT */
313 gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
314 if (gsel < 0) {
315 ret = gsel;
316 goto done;
317 }
318
319 /*
320 * Register a single group function where the 'data' is an array PSEL
321 * register values read from DT.
322 */
323 pin_fn[0] = np->name;
324 fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
325 psel_val);
326 if (fsel < 0) {
327 ret = fsel;
328 goto remove_group;
329 }
330
331 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
332 maps[idx].data.mux.group = np->name;
333 maps[idx].data.mux.function = np->name;
334 idx++;
335
336 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
337 ret = 0;
338 goto done;
339
340 remove_group:
341 pinctrl_generic_remove_group(pctldev, gsel);
342 done:
343 *index = idx;
344 kfree(configs);
345 return ret;
346 }
347
rzv2m_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned int num_maps)348 static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev,
349 struct pinctrl_map *map,
350 unsigned int num_maps)
351 {
352 unsigned int i;
353
354 if (!map)
355 return;
356
357 for (i = 0; i < num_maps; ++i) {
358 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
359 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
360 kfree(map[i].data.configs.configs);
361 }
362 kfree(map);
363 }
364
rzv2m_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)365 static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
366 struct device_node *np,
367 struct pinctrl_map **map,
368 unsigned int *num_maps)
369 {
370 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
371 struct device_node *child;
372 unsigned int index;
373 int ret;
374
375 *map = NULL;
376 *num_maps = 0;
377 index = 0;
378
379 for_each_child_of_node(np, child) {
380 ret = rzv2m_dt_subnode_to_map(pctldev, child, map,
381 num_maps, &index);
382 if (ret < 0) {
383 of_node_put(child);
384 goto done;
385 }
386 }
387
388 if (*num_maps == 0) {
389 ret = rzv2m_dt_subnode_to_map(pctldev, np, map,
390 num_maps, &index);
391 if (ret < 0)
392 goto done;
393 }
394
395 if (*num_maps)
396 return 0;
397
398 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
399 ret = -EINVAL;
400
401 done:
402 rzv2m_dt_free_map(pctldev, *map, *num_maps);
403
404 return ret;
405 }
406
rzv2m_validate_gpio_pin(struct rzv2m_pinctrl * pctrl,u32 cfg,u32 port,u8 bit)407 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl,
408 u32 cfg, u32 port, u8 bit)
409 {
410 u8 pincount = RZV2M_GPIO_PORT_GET_PINCNT(cfg);
411 u32 port_index = RZV2M_GPIO_PORT_GET_INDEX(cfg);
412 u32 data;
413
414 if (bit >= pincount || port >= pctrl->data->n_port_pins)
415 return -EINVAL;
416
417 data = pctrl->data->port_pin_configs[port];
418 if (port_index != RZV2M_GPIO_PORT_GET_INDEX(data))
419 return -EINVAL;
420
421 return 0;
422 }
423
rzv2m_rmw_pin_config(struct rzv2m_pinctrl * pctrl,u32 offset,u8 shift,u32 mask,u32 val)424 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset,
425 u8 shift, u32 mask, u32 val)
426 {
427 void __iomem *addr = pctrl->base + offset;
428 unsigned long flags;
429 u32 reg;
430
431 spin_lock_irqsave(&pctrl->lock, flags);
432 reg = readl(addr) & ~(mask << shift);
433 writel(reg | (val << shift), addr);
434 spin_unlock_irqrestore(&pctrl->lock, flags);
435 }
436
rzv2m_pinctrl_pinconf_get(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * config)437 static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
438 unsigned int _pin,
439 unsigned long *config)
440 {
441 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
442 enum pin_config_param param = pinconf_to_config_param(*config);
443 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
444 unsigned int *pin_data = pin->drv_data;
445 unsigned int arg = 0;
446 u32 port;
447 u32 cfg;
448 u8 bit;
449 u32 val;
450
451 if (!pin_data)
452 return -EINVAL;
453
454 if (*pin_data & RZV2M_SINGLE_PIN) {
455 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
456 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
457 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
458 } else {
459 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
460 port = RZV2M_PIN_ID_TO_PORT(_pin);
461 bit = RZV2M_PIN_ID_TO_PIN(_pin);
462
463 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
464 return -EINVAL;
465 }
466
467 switch (param) {
468 case PIN_CONFIG_BIAS_DISABLE:
469 case PIN_CONFIG_BIAS_PULL_UP:
470 case PIN_CONFIG_BIAS_PULL_DOWN: {
471 enum pin_config_param bias;
472
473 if (!(cfg & PIN_CFG_BIAS))
474 return -EINVAL;
475
476 /* PUPD uses 2-bits per pin */
477 bit *= 2;
478
479 switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) {
480 case 0:
481 bias = PIN_CONFIG_BIAS_PULL_DOWN;
482 break;
483 case 2:
484 bias = PIN_CONFIG_BIAS_PULL_UP;
485 break;
486 default:
487 bias = PIN_CONFIG_BIAS_DISABLE;
488 }
489
490 if (bias != param)
491 return -EINVAL;
492 break;
493 }
494
495 case PIN_CONFIG_DRIVE_STRENGTH_UA:
496 if (!(cfg & PIN_CFG_DRV))
497 return -EINVAL;
498
499 /* DRV uses 2-bits per pin */
500 bit *= 2;
501
502 val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK;
503
504 switch (cfg & PIN_CFG_GRP_MASK) {
505 case PIN_CFG_GRP_1_8V_2:
506 arg = drv_1_8V_group2_uA[val];
507 break;
508 case PIN_CFG_GRP_1_8V_3:
509 arg = drv_1_8V_group3_uA[val];
510 break;
511 case PIN_CFG_GRP_SWIO_2:
512 arg = drv_SWIO_group2_3_3V_uA[val];
513 break;
514 case PIN_CFG_GRP_SWIO_1:
515 case PIN_CFG_GRP_3_3V:
516 arg = drv_3_3V_group_uA[val];
517 break;
518 default:
519 return -EINVAL;
520 }
521
522 break;
523
524 case PIN_CONFIG_SLEW_RATE:
525 if (!(cfg & PIN_CFG_SLEW))
526 return -EINVAL;
527
528 arg = readl(pctrl->base + SR(port)) & BIT(bit);
529 break;
530
531 default:
532 return -ENOTSUPP;
533 }
534
535 *config = pinconf_to_config_packed(param, arg);
536
537 return 0;
538 };
539
rzv2m_pinctrl_pinconf_set(struct pinctrl_dev * pctldev,unsigned int _pin,unsigned long * _configs,unsigned int num_configs)540 static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
541 unsigned int _pin,
542 unsigned long *_configs,
543 unsigned int num_configs)
544 {
545 struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
546 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
547 unsigned int *pin_data = pin->drv_data;
548 enum pin_config_param param;
549 u32 port;
550 unsigned int i;
551 u32 cfg;
552 u8 bit;
553 u32 val;
554
555 if (!pin_data)
556 return -EINVAL;
557
558 if (*pin_data & RZV2M_SINGLE_PIN) {
559 port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
560 cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
561 bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
562 } else {
563 cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
564 port = RZV2M_PIN_ID_TO_PORT(_pin);
565 bit = RZV2M_PIN_ID_TO_PIN(_pin);
566
567 if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
568 return -EINVAL;
569 }
570
571 for (i = 0; i < num_configs; i++) {
572 param = pinconf_to_config_param(_configs[i]);
573 switch (param) {
574 case PIN_CONFIG_BIAS_DISABLE:
575 case PIN_CONFIG_BIAS_PULL_UP:
576 case PIN_CONFIG_BIAS_PULL_DOWN:
577 if (!(cfg & PIN_CFG_BIAS))
578 return -EINVAL;
579
580 /* PUPD uses 2-bits per pin */
581 bit *= 2;
582
583 switch (param) {
584 case PIN_CONFIG_BIAS_PULL_DOWN:
585 val = 0;
586 break;
587 case PIN_CONFIG_BIAS_PULL_UP:
588 val = 2;
589 break;
590 default:
591 val = 1;
592 }
593
594 rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val);
595 break;
596
597 case PIN_CONFIG_DRIVE_STRENGTH_UA: {
598 unsigned int arg = pinconf_to_config_argument(_configs[i]);
599 const unsigned int *drv_strengths;
600 unsigned int index;
601
602 if (!(cfg & PIN_CFG_DRV))
603 return -EINVAL;
604
605 switch (cfg & PIN_CFG_GRP_MASK) {
606 case PIN_CFG_GRP_1_8V_2:
607 drv_strengths = drv_1_8V_group2_uA;
608 break;
609 case PIN_CFG_GRP_1_8V_3:
610 drv_strengths = drv_1_8V_group3_uA;
611 break;
612 case PIN_CFG_GRP_SWIO_2:
613 drv_strengths = drv_SWIO_group2_3_3V_uA;
614 break;
615 case PIN_CFG_GRP_SWIO_1:
616 case PIN_CFG_GRP_3_3V:
617 drv_strengths = drv_3_3V_group_uA;
618 break;
619 default:
620 return -EINVAL;
621 }
622
623 for (index = 0; index < 4; index++) {
624 if (arg == drv_strengths[index])
625 break;
626 }
627 if (index >= 4)
628 return -EINVAL;
629
630 /* DRV uses 2-bits per pin */
631 bit *= 2;
632
633 rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index);
634 break;
635 }
636
637 case PIN_CONFIG_SLEW_RATE: {
638 unsigned int arg = pinconf_to_config_argument(_configs[i]);
639
640 if (!(cfg & PIN_CFG_SLEW))
641 return -EINVAL;
642
643 rzv2m_writel_we(pctrl->base + SR(port), bit, !arg);
644 break;
645 }
646
647 default:
648 return -EOPNOTSUPP;
649 }
650 }
651
652 return 0;
653 }
654
rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * configs,unsigned int num_configs)655 static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
656 unsigned int group,
657 unsigned long *configs,
658 unsigned int num_configs)
659 {
660 const unsigned int *pins;
661 unsigned int i, npins;
662 int ret;
663
664 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
665 if (ret)
666 return ret;
667
668 for (i = 0; i < npins; i++) {
669 ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs,
670 num_configs);
671 if (ret)
672 return ret;
673 }
674
675 return 0;
676 };
677
rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev * pctldev,unsigned int group,unsigned long * config)678 static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
679 unsigned int group,
680 unsigned long *config)
681 {
682 const unsigned int *pins;
683 unsigned int i, npins, prev_config = 0;
684 int ret;
685
686 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
687 if (ret)
688 return ret;
689
690 for (i = 0; i < npins; i++) {
691 ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config);
692 if (ret)
693 return ret;
694
695 /* Check config matches previous pins */
696 if (i && prev_config != *config)
697 return -EOPNOTSUPP;
698
699 prev_config = *config;
700 }
701
702 return 0;
703 };
704
705 static const struct pinctrl_ops rzv2m_pinctrl_pctlops = {
706 .get_groups_count = pinctrl_generic_get_group_count,
707 .get_group_name = pinctrl_generic_get_group_name,
708 .get_group_pins = pinctrl_generic_get_group_pins,
709 .dt_node_to_map = rzv2m_dt_node_to_map,
710 .dt_free_map = rzv2m_dt_free_map,
711 };
712
713 static const struct pinmux_ops rzv2m_pinctrl_pmxops = {
714 .get_functions_count = pinmux_generic_get_function_count,
715 .get_function_name = pinmux_generic_get_function_name,
716 .get_function_groups = pinmux_generic_get_function_groups,
717 .set_mux = rzv2m_pinctrl_set_mux,
718 .strict = true,
719 };
720
721 static const struct pinconf_ops rzv2m_pinctrl_confops = {
722 .is_generic = true,
723 .pin_config_get = rzv2m_pinctrl_pinconf_get,
724 .pin_config_set = rzv2m_pinctrl_pinconf_set,
725 .pin_config_group_set = rzv2m_pinctrl_pinconf_group_set,
726 .pin_config_group_get = rzv2m_pinctrl_pinconf_group_get,
727 .pin_config_config_dbg_show = pinconf_generic_dump_config,
728 };
729
rzv2m_gpio_request(struct gpio_chip * chip,unsigned int offset)730 static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset)
731 {
732 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
733 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
734 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
735 int ret;
736
737 ret = pinctrl_gpio_request(chip->base + offset);
738 if (ret)
739 return ret;
740
741 rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0);
742
743 return 0;
744 }
745
rzv2m_gpio_set_direction(struct rzv2m_pinctrl * pctrl,u32 port,u8 bit,bool output)746 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port,
747 u8 bit, bool output)
748 {
749 rzv2m_writel_we(pctrl->base + OE(port), bit, output);
750 rzv2m_writel_we(pctrl->base + IE(port), bit, !output);
751 }
752
rzv2m_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)753 static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
754 {
755 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
756 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
757 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
758
759 if (!(readl(pctrl->base + IE(port)) & BIT(bit)))
760 return GPIO_LINE_DIRECTION_OUT;
761
762 return GPIO_LINE_DIRECTION_IN;
763 }
764
rzv2m_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)765 static int rzv2m_gpio_direction_input(struct gpio_chip *chip,
766 unsigned int offset)
767 {
768 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
769 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
770 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
771
772 rzv2m_gpio_set_direction(pctrl, port, bit, false);
773
774 return 0;
775 }
776
rzv2m_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)777 static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
778 int value)
779 {
780 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
781 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
782 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
783
784 rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
785 }
786
rzv2m_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)787 static int rzv2m_gpio_direction_output(struct gpio_chip *chip,
788 unsigned int offset, int value)
789 {
790 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
791 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
792 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
793
794 rzv2m_gpio_set(chip, offset, value);
795 rzv2m_gpio_set_direction(pctrl, port, bit, true);
796
797 return 0;
798 }
799
rzv2m_gpio_get(struct gpio_chip * chip,unsigned int offset)800 static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset)
801 {
802 struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
803 u32 port = RZV2M_PIN_ID_TO_PORT(offset);
804 u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
805 int direction = rzv2m_gpio_get_direction(chip, offset);
806
807 if (direction == GPIO_LINE_DIRECTION_IN)
808 return !!(readl(pctrl->base + DI(port)) & BIT(bit));
809 else
810 return !!(readl(pctrl->base + DO(port)) & BIT(bit));
811 }
812
rzv2m_gpio_free(struct gpio_chip * chip,unsigned int offset)813 static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset)
814 {
815 pinctrl_gpio_free(chip->base + offset);
816
817 /*
818 * Set the GPIO as an input to ensure that the next GPIO request won't
819 * drive the GPIO pin as an output.
820 */
821 rzv2m_gpio_direction_input(chip, offset);
822 }
823
824 static const char * const rzv2m_gpio_names[] = {
825 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
826 "P0_8", "P0_9", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15",
827 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
828 "P1_8", "P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15",
829 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
830 "P2_8", "P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15",
831 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
832 "P3_8", "P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15",
833 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
834 "P4_8", "P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15",
835 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
836 "P5_8", "P5_9", "P5_10", "P5_11", "P5_12", "P5_13", "P5_14", "P5_15",
837 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
838 "P6_8", "P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15",
839 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
840 "P7_8", "P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15",
841 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
842 "P8_8", "P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15",
843 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
844 "P9_8", "P9_9", "P9_10", "P9_11", "P9_12", "P9_13", "P9_14", "P9_15",
845 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
846 "P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14", "P10_15",
847 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
848 "P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14", "P11_15",
849 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
850 "P12_8", "P12_9", "P12_10", "P12_11", "P12_12", "P12_13", "P12_14", "P12_15",
851 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
852 "P13_8", "P13_9", "P13_10", "P13_11", "P13_12", "P13_13", "P13_14", "P13_15",
853 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
854 "P14_8", "P14_9", "P14_10", "P14_11", "P14_12", "P14_13", "P14_14", "P14_15",
855 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
856 "P15_8", "P15_9", "P15_10", "P15_11", "P15_12", "P15_13", "P15_14", "P15_15",
857 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
858 "P16_8", "P16_9", "P16_10", "P16_11", "P16_12", "P16_13", "P16_14", "P16_15",
859 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
860 "P17_8", "P17_9", "P17_10", "P17_11", "P17_12", "P17_13", "P17_14", "P17_15",
861 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
862 "P18_8", "P18_9", "P18_10", "P18_11", "P18_12", "P18_13", "P18_14", "P18_15",
863 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
864 "P19_8", "P19_9", "P19_10", "P19_11", "P19_12", "P19_13", "P19_14", "P19_15",
865 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
866 "P20_8", "P20_9", "P20_10", "P20_11", "P20_12", "P20_13", "P20_14", "P20_15",
867 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
868 "P21_8", "P21_9", "P21_10", "P21_11", "P21_12", "P21_13", "P21_14", "P21_15",
869 };
870
871 static const u32 rzv2m_gpio_configs[] = {
872 RZV2M_GPIO_PORT_PACK(14, 0, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
873 RZV2M_GPIO_PORT_PACK(16, 1, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
874 RZV2M_GPIO_PORT_PACK(8, 2, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
875 RZV2M_GPIO_PORT_PACK(16, 3, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
876 RZV2M_GPIO_PORT_PACK(8, 4, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
877 RZV2M_GPIO_PORT_PACK(4, 5, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
878 RZV2M_GPIO_PORT_PACK(12, 6, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
879 RZV2M_GPIO_PORT_PACK(6, 7, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
880 RZV2M_GPIO_PORT_PACK(8, 8, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
881 RZV2M_GPIO_PORT_PACK(8, 9, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
882 RZV2M_GPIO_PORT_PACK(9, 10, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
883 RZV2M_GPIO_PORT_PACK(9, 11, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
884 RZV2M_GPIO_PORT_PACK(4, 12, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
885 RZV2M_GPIO_PORT_PACK(12, 13, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
886 RZV2M_GPIO_PORT_PACK(8, 14, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
887 RZV2M_GPIO_PORT_PACK(16, 15, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
888 RZV2M_GPIO_PORT_PACK(14, 16, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
889 RZV2M_GPIO_PORT_PACK(1, 17, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
890 RZV2M_GPIO_PORT_PACK(0, 18, 0),
891 RZV2M_GPIO_PORT_PACK(0, 19, 0),
892 RZV2M_GPIO_PORT_PACK(3, 20, PIN_CFG_GRP_1_8V_2 | PIN_CFG_DRV),
893 RZV2M_GPIO_PORT_PACK(1, 21, PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW),
894 };
895
896 static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = {
897 { "NAWPN", RZV2M_SINGLE_PIN_PACK(0,
898 (PIN_CFG_GRP_SWIO_2 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
899 { "IM0CLK", RZV2M_SINGLE_PIN_PACK(1,
900 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
901 { "IM1CLK", RZV2M_SINGLE_PIN_PACK(2,
902 (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
903 { "DETDO", RZV2M_SINGLE_PIN_PACK(5,
904 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
905 { "DETMS", RZV2M_SINGLE_PIN_PACK(6,
906 (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
907 { "PCRSTOUTB", RZV2M_SINGLE_PIN_PACK(12,
908 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
909 { "USPWEN", RZV2M_SINGLE_PIN_PACK(14,
910 (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
911 };
912
rzv2m_gpio_register(struct rzv2m_pinctrl * pctrl)913 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl)
914 {
915 struct device_node *np = pctrl->dev->of_node;
916 struct gpio_chip *chip = &pctrl->gpio_chip;
917 const char *name = dev_name(pctrl->dev);
918 struct of_phandle_args of_args;
919 int ret;
920
921 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
922 if (ret) {
923 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
924 return ret;
925 }
926
927 if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
928 of_args.args[2] != pctrl->data->n_port_pins) {
929 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
930 return -EINVAL;
931 }
932
933 chip->names = pctrl->data->port_pins;
934 chip->request = rzv2m_gpio_request;
935 chip->free = rzv2m_gpio_free;
936 chip->get_direction = rzv2m_gpio_get_direction;
937 chip->direction_input = rzv2m_gpio_direction_input;
938 chip->direction_output = rzv2m_gpio_direction_output;
939 chip->get = rzv2m_gpio_get;
940 chip->set = rzv2m_gpio_set;
941 chip->label = name;
942 chip->parent = pctrl->dev;
943 chip->owner = THIS_MODULE;
944 chip->base = -1;
945 chip->ngpio = of_args.args[2];
946
947 pctrl->gpio_range.id = 0;
948 pctrl->gpio_range.pin_base = 0;
949 pctrl->gpio_range.base = 0;
950 pctrl->gpio_range.npins = chip->ngpio;
951 pctrl->gpio_range.name = chip->label;
952 pctrl->gpio_range.gc = chip;
953 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
954 if (ret) {
955 dev_err(pctrl->dev, "failed to add GPIO controller\n");
956 return ret;
957 }
958
959 dev_dbg(pctrl->dev, "Registered gpio controller\n");
960
961 return 0;
962 }
963
rzv2m_pinctrl_register(struct rzv2m_pinctrl * pctrl)964 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl)
965 {
966 struct pinctrl_pin_desc *pins;
967 unsigned int i, j;
968 u32 *pin_data;
969 int ret;
970
971 pctrl->desc.name = DRV_NAME;
972 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
973 pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops;
974 pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops;
975 pctrl->desc.confops = &rzv2m_pinctrl_confops;
976 pctrl->desc.owner = THIS_MODULE;
977
978 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
979 if (!pins)
980 return -ENOMEM;
981
982 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
983 sizeof(*pin_data), GFP_KERNEL);
984 if (!pin_data)
985 return -ENOMEM;
986
987 pctrl->pins = pins;
988 pctrl->desc.pins = pins;
989
990 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
991 pins[i].number = i;
992 pins[i].name = pctrl->data->port_pins[i];
993 if (i && !(i % RZV2M_PINS_PER_PORT))
994 j++;
995 pin_data[i] = pctrl->data->port_pin_configs[j];
996 pins[i].drv_data = &pin_data[i];
997 }
998
999 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
1000 unsigned int index = pctrl->data->n_port_pins + i;
1001
1002 pins[index].number = index;
1003 pins[index].name = pctrl->data->dedicated_pins[i].name;
1004 pin_data[index] = pctrl->data->dedicated_pins[i].config;
1005 pins[index].drv_data = &pin_data[index];
1006 }
1007
1008 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1009 &pctrl->pctl);
1010 if (ret) {
1011 dev_err(pctrl->dev, "pinctrl registration failed\n");
1012 return ret;
1013 }
1014
1015 ret = pinctrl_enable(pctrl->pctl);
1016 if (ret) {
1017 dev_err(pctrl->dev, "pinctrl enable failed\n");
1018 return ret;
1019 }
1020
1021 ret = rzv2m_gpio_register(pctrl);
1022 if (ret) {
1023 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1024 return ret;
1025 }
1026
1027 return 0;
1028 }
1029
rzv2m_pinctrl_clk_disable(void * data)1030 static void rzv2m_pinctrl_clk_disable(void *data)
1031 {
1032 clk_disable_unprepare(data);
1033 }
1034
rzv2m_pinctrl_probe(struct platform_device * pdev)1035 static int rzv2m_pinctrl_probe(struct platform_device *pdev)
1036 {
1037 struct rzv2m_pinctrl *pctrl;
1038 int ret;
1039
1040 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1041 if (!pctrl)
1042 return -ENOMEM;
1043
1044 pctrl->dev = &pdev->dev;
1045
1046 pctrl->data = of_device_get_match_data(&pdev->dev);
1047 if (!pctrl->data)
1048 return -EINVAL;
1049
1050 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1051 if (IS_ERR(pctrl->base))
1052 return PTR_ERR(pctrl->base);
1053
1054 pctrl->clk = devm_clk_get(pctrl->dev, NULL);
1055 if (IS_ERR(pctrl->clk)) {
1056 ret = PTR_ERR(pctrl->clk);
1057 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
1058 return ret;
1059 }
1060
1061 spin_lock_init(&pctrl->lock);
1062
1063 platform_set_drvdata(pdev, pctrl);
1064
1065 ret = clk_prepare_enable(pctrl->clk);
1066 if (ret) {
1067 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
1068 return ret;
1069 }
1070
1071 ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable,
1072 pctrl->clk);
1073 if (ret) {
1074 dev_err(pctrl->dev,
1075 "failed to register GPIO clk disable action, %i\n",
1076 ret);
1077 return ret;
1078 }
1079
1080 ret = rzv2m_pinctrl_register(pctrl);
1081 if (ret)
1082 return ret;
1083
1084 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1085 return 0;
1086 }
1087
1088 static struct rzv2m_pinctrl_data r9a09g011_data = {
1089 .port_pins = rzv2m_gpio_names,
1090 .port_pin_configs = rzv2m_gpio_configs,
1091 .dedicated_pins = rzv2m_dedicated_pins,
1092 .n_port_pins = ARRAY_SIZE(rzv2m_gpio_configs) * RZV2M_PINS_PER_PORT,
1093 .n_dedicated_pins = ARRAY_SIZE(rzv2m_dedicated_pins),
1094 };
1095
1096 static const struct of_device_id rzv2m_pinctrl_of_table[] = {
1097 {
1098 .compatible = "renesas,r9a09g011-pinctrl",
1099 .data = &r9a09g011_data,
1100 },
1101 { /* sentinel */ }
1102 };
1103
1104 static struct platform_driver rzv2m_pinctrl_driver = {
1105 .driver = {
1106 .name = DRV_NAME,
1107 .of_match_table = of_match_ptr(rzv2m_pinctrl_of_table),
1108 },
1109 .probe = rzv2m_pinctrl_probe,
1110 };
1111
rzv2m_pinctrl_init(void)1112 static int __init rzv2m_pinctrl_init(void)
1113 {
1114 return platform_driver_register(&rzv2m_pinctrl_driver);
1115 }
1116 core_initcall(rzv2m_pinctrl_init);
1117
1118 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1119 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/V2M");
1120 MODULE_LICENSE("GPL");
1121