1 /* 2 * Copyright (C) 2015-2020 Alibaba Group Holding Limited 3 */ 4 #ifndef __PLAT_ADDR_MAP_BEST2001_H__ 5 #define __PLAT_ADDR_MAP_BEST2001_H__ 6 7 #ifdef __cplusplus 8 extern "C" { 9 #endif 10 11 #define ROM_BASE 0x00000000 12 #define ROMD_BASE 0x24000000 13 14 #ifndef ROM_SIZE 15 #define ROM_SIZE 0x00010000 16 #endif 17 18 #define RAM0_BASE 0x20000000 19 #define RAMX0_BASE 0x00200000 20 #define RAM1_BASE 0x20040000 21 #define RAMX1_BASE 0x00240000 22 #define RAM2_BASE 0x20060000 23 #define RAMX2_BASE 0x00260000 24 #define RAM3_BASE 0x20080000 25 #define RAMX3_BASE 0x00280000 26 #define RAM4_BASE 0x200A0000 27 #define RAMX4_BASE 0x002A0000 28 #define RAM5_BASE 0x200C0000 29 #define RAMX5_BASE 0x002C0000 30 #define RAM6_BASE 0x200E0000 31 #define RAMX6_BASE 0x002E0000 32 #define RAM7_BASE 0x20100000 33 #define RAMX7_BASE 0x00300000 34 #define RAM8_BASE 0x20180000 35 #define RAMX8_BASE 0x00380000 36 #define RAM9_BASE 0x20200000 37 #define RAMX9_BASE 0x00400000 38 #define RAM_BASE RAM0_BASE 39 #define RAMX_BASE RAMX0_BASE 40 41 #define RAM9_SIZE 0x00080000 42 43 #ifdef LARGE_RAM 44 #ifndef RAMCP_BASE 45 #define RAMCP_BASE RAM9_BASE 46 #endif 47 #ifndef RAMCP_SIZE 48 #define RAMCP_SIZE 0x30000 49 #endif 50 #ifndef RAMCPX_BASE 51 #define RAMCPX_BASE (RAMX9_BASE + RAMCP_SIZE) 52 #endif 53 #ifndef RAMCPX_SIZE 54 #define RAMCPX_SIZE (RAM9_SIZE - RAMCP_SIZE) 55 #endif 56 #else /*LARGE_RAM*/ 57 #ifndef RAMCP_BASE 58 #define RAMCP_BASE RAM2_BASE 59 #endif 60 #ifndef RAMCP_SIZE 61 #define RAMCP_SIZE (RAM3_BASE - RAMCP_BASE) 62 #endif 63 #ifndef RAMCPX_BASE 64 #define RAMCPX_BASE RAMX1_BASE 65 #endif 66 #ifndef RAMCPX_SIZE 67 #define RAMCPX_SIZE (RAMX2_BASE - RAMCPX_BASE) 68 #endif 69 70 #endif /*LARGE_RAM*/ 71 72 #define MAX_RAM_SIZE (RAM9_BASE + RAM9_SIZE - RAM0_BASE) // 0x00280000 73 74 #ifndef RAM_SIZE 75 #ifdef LARGE_RAM 76 #ifdef NO_RAMCP 77 #define RAM_SIZE MAX_RAM_SIZE 78 #else 79 #define RAM_SIZE (RAM9_BASE - RAM0_BASE) // 0x00080000 80 #endif 81 #else 82 #ifdef NO_RAMCP 83 #define RAM_SIZE (RAM3_BASE - RAM0_BASE) // 0x00080000 84 #else 85 #define RAM_SIZE (RAM1_BASE - RAM0_BASE) // 0x00040000 86 #endif 87 #endif 88 #endif 89 90 #ifndef MCU_PSRAMUHS_SIZE 91 #define MCU_PSRAMUHS_SIZE (0) 92 #endif 93 94 #define FLASH_BASE 0x2C000000 95 #define FLASH_NC_BASE 0x28000000 96 #define FLASHX_BASE 0x0C000000 97 #define FLASHX_NC_BASE 0x08000000 98 99 #define PSRAM_BASE 0x34000000 100 #define PSRAM_NC_BASE 0x30000000 101 #define PSRAMX_BASE 0x14000000 102 #define PSRAMX_NC_BASE 0x10000000 103 104 #define PSRAMUHS_BASE 0x3C000000 105 #define PSRAMUHS_NC_BASE 0x38000000 106 #define PSRAMUHSX_BASE 0x1C000000 107 #define PSRAMUHSX_NC_BASE 0x18000000 108 109 #define ICACHE_CTRL_BASE 0x07FFE000 110 #define ICACHECP_CTRL_BASE 0x07FFE000 111 #define DCACHE_CTRL_BASE 0x27FFE000 112 #define DCACHECP_CTRL_BASE 0x27FFE000 113 114 #define CMU_BASE 0x40000000 115 #define MCU_WDT_BASE 0x40001000 116 #define MCU_TIMER0_BASE 0x40002000 117 #define MCU_TIMER1_BASE 0x40003000 118 #define MCU_TIMER2_BASE 0x40004000 119 #define I2C0_BASE 0x40005000 120 #define I2C1_BASE 0x40006000 121 #define SPI_BASE 0x40007000 122 #define SPILCD_BASE 0x40008000 123 #define ISPI_BASE 0x40009000 124 #define SPIPHY_BASE 0x4000A000 125 #define UART0_BASE 0x4000B000 126 #define UART1_BASE 0x4000C000 127 #define UART2_BASE 0x4000D000 128 #define BTPCM_BASE 0x4000E000 129 #define I2S0_BASE 0x4000F000 130 #define SPDIF0_BASE 0x40010000 131 #define TRANSQW_BASE 0x40011000 132 #define TRANSQD_BASE 0x40012000 133 #define TRNG_BASE 0x40013000 134 #define SEC_ENG_BASE 0x40020000 135 136 #define AON_CMU_BASE 0x40080000 137 #define AON_GPIO_BASE 0x40081000 138 #define AON_WDT_BASE 0x40082000 139 #define AON_PWM_BASE 0x40083000 140 #define AON_TIMER_BASE 0x40084000 141 #define AON_GPIOAUX_BASE 0x40085000 142 #define AON_IOMUX_BASE 0x40086000 143 #define AON_SPIDPD_BASE 0x40087000 144 145 #define CHECKSUM_BASE 0x40100000 146 #define CRC_BASE 0x40108000 147 #define SDMMC_BASE 0x40110000 148 #define BES2001_AUDMA_BASE 0x40120000 149 #define BES2001_GPDMA_BASE 0x40130000 150 #define FLASH_CTRL_BASE 0x40140000 151 #define PSRAM_CTRL_BASE 0x40150000 152 #define I2C_SLAVE_BASE 0x40160000 153 #define WFDUMP_BASE 0x40170000 154 #define USB_BASE 0x40180000 155 #define SEDMA_BASE 0x401D0000 156 #define BTDUMP_BASE 0x401E0000 157 #define PSRAMUHS_CTRL_BASE 0x401F0000 158 159 #define CODEC_BASE 0x40300000 160 161 #define PATCH_ENTRY_NUM 8 162 #define PATCH_CTRL_BASE 0x000FFE00 163 #define PATCH_DATA_BASE 0x000FFF00 164 #define WIFI_PATCH_CTRL_BASE 0x6007fe00 165 #define WIFI_PATCH_DATA_BASE 0x6007ff00 166 167 #define BT_SUBSYS_BASE 0xA0000000 168 #define BT_RAM_BASE 0xC0000000 169 #define BT_UART_BASE 0xD0300000 170 #define BT_CMU_BASE 0xD0330000 171 172 #define WIFI_SUBSYS_BASE 0x60000000 173 #define WIFI_RAM_BASE 0x80000000 174 #define WIFI_PAS_BASE 0x82000000 175 #define WIFI_TRANSQM_BASE 0x9000A000 176 177 #define DSP_SUBSYS_BASE 0x50000000 178 179 #define DSP_BOOT_BASE 0x00000000 180 #define DSP_BOOT_SIZE (24 * 4) 181 182 #define DSP_RAM0_BASE 0x50000000 183 #define DSP_RAM1_BASE 0x50080000 184 #define DSP_RAM2_BASE 0x50100000 185 #define DSP_RAM3_BASE 0x50180000 186 #define DSP_RAM4_BASE 0x50200000 187 #define DSP_RAM5_BASE 0x50220000 188 #define DSP_RAM_BASE DSP_RAM0_BASE 189 190 #define DSP_RAM5_SIZE 0x00020000 191 192 #define MAX_DSP_RAM_SIZE (DSP_RAM5_BASE + DSP_RAM5_SIZE - DSP_RAM0_BASE) 193 194 #ifndef DSP_RAM_SIZE 195 #ifdef LARGE_DSP_RAM 196 #define DSP_RAM_SIZE MAX_DSP_RAM_SIZE 197 #else /*LARGE_DSP_RAM*/ 198 #ifdef FPGA 199 #define DSP_RAM_SIZE (DSP_RAM1_BASE - DSP_RAM0_BASE) 200 #else /*FPGA*/ 201 #define DSP_RAM_SIZE (DSP_RAM4_BASE - DSP_RAM0_BASE) 202 #endif /*FPGA*/ 203 #endif /*LARGE_DSP_RAM*/ 204 #endif 205 206 #ifndef DSP_PSRAMUHS_SIZE 207 #define DSP_PSRAMUHS_SIZE (0) 208 #endif 209 210 #define DSP_PSRAMUHS_BASE (PSRAMUHS_BASE) 211 #define DSP_PSRAMUHSX_BASE (PSRAMUHSX_BASE) 212 213 #define MCU_PSRAMUHS_BASE (PSRAMUHS_BASE + DSP_PSRAMUHS_SIZE) 214 #define MCU_PSRAMUHS_NC_BASE (PSRAMUHS_NC_BASE + DSP_PSRAMUHS_SIZE) 215 #define MCU_PSRAMUHSX_BASE (PSRAMUHSX_BASE + DSP_PSRAMUHS_SIZE) 216 217 #define DSP_BOOT_REG 0x58000000 218 #define DSP_WDT_BASE 0x58001000 219 #define DSP_TIMER0_BASE 0x58002000 220 #define DSP_TIMER1_BASE 0x58003000 221 #define DSP_TRANSQM_BASE 0x58004000 222 #define DSP_TIMESTAMP_GEN_BASE 0x58020000 223 224 #define DSP_DEBUGSYS_APB_BASE 0x58040000 225 226 #define DSP_XDMA_BASE 0x58200000 227 228 #define GIC_DISTRIBUTOR_BASE 0x58301000 229 #define GIC_INTERFACE_BASE 0x58302000 230 231 #define IOMUX_BASE AON_IOMUX_BASE 232 #define GPIO_BASE AON_GPIO_BASE 233 #define GPIOAUX_BASE AON_GPIOAUX_BASE 234 #define PWM_BASE AON_PWM_BASE 235 #define SPIDPD_BASE AON_SPIDPD_BASE 236 237 #ifdef CHIP_HAAS1000_DSP 238 #define TIMER0_BASE DSP_TIMER0_BASE 239 #define TIMER1_BASE DSP_TIMER1_BASE 240 #define TRANSQ0_BASE TRANSQW_BASE 241 #define TRANSQ0_PEER_BASE WIFI_TRANSQM_BASE 242 #define TRANSQ1_BASE DSP_TRANSQM_BASE 243 #define TRANSQ1_PEER_BASE TRANSQD_BASE 244 #define WDT_BASE DSP_WDT_BASE 245 #else 246 #define TIMER0_BASE MCU_TIMER0_BASE 247 #define TIMER1_BASE MCU_TIMER1_BASE 248 #define TIMER2_BASE MCU_TIMER2_BASE 249 #define TRANSQ0_BASE TRANSQW_BASE 250 #define TRANSQ0_PEER_BASE WIFI_TRANSQM_BASE 251 #define TRANSQ1_BASE TRANSQD_BASE 252 #define TRANSQ1_PEER_BASE DSP_TRANSQM_BASE 253 #define WDT_BASE AON_WDT_BASE 254 #endif 255 256 #ifndef DSP_USE_AUDMA 257 #define AUDMA_BASE BES2001_AUDMA_BASE 258 #define GPDMA_BASE BES2001_GPDMA_BASE 259 #else /*DSP_USE_AUDMA*/ 260 #ifdef CHIP_HAAS1000_DSP 261 #define AUDMA_BASE BES2001_AUDMA_BASE //A7 use AUDMA 262 #else 263 #define AUDMA_BASE BES2001_GPDMA_BASE //MCU use GPDMA 264 #endif 265 #endif /*DSP_USE_AUDMA*/ 266 267 /* For module features */ 268 #define SEC_ENG_HAS_HASH 269 270 /* For linker scripts */ 271 272 #define VECTOR_SECTION_SIZE 360 273 #define REBOOT_PARAM_SECTION_SIZE 64 274 #define ROM_BUILD_INFO_SECTION_SIZE 40 275 #define ROM_EXPORT_FN_SECTION_SIZE 128 276 277 #define PSRAMUHSX_TO_PSRAMUHS(d) ((d) - PSRAMUHSX_BASE + PSRAMUHS_BASE) 278 #define PSRAMUHS_TO_PSRAMUHSX(d) ((d) - PSRAMUHS_BASE + PSRAMUHSX_BASE) 279 #define PSRAMUHS_TO_PSRAMUHSNC(d) ((d) - PSRAMUHS_BASE + PSRAMUHS_NC_BASE) 280 281 #define BT_INTESYS_MEM_OFFSET 0x00000000 282 283 #ifdef __cplusplus 284 } 285 #endif 286 287 #endif 288