1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Applied Micro X-Gene SoC Ethernet v2 Driver
4 *
5 * Copyright (c) 2017, Applied Micro Circuits Corporation
6 * Author(s): Iyappan Subramanian <isubramanian@apm.com>
7 * Keyur Chudgar <kchudgar@apm.com>
8 */
9
10 #ifndef __XGENE_ENET_V2_MAC_H__
11 #define __XGENE_ENET_V2_MAC_H__
12
13 /* Register offsets */
14 #define MAC_CONFIG_1 0xa000
15 #define MAC_CONFIG_2 0xa004
16 #define MII_MGMT_CONFIG 0xa020
17 #define MII_MGMT_COMMAND 0xa024
18 #define MII_MGMT_ADDRESS 0xa028
19 #define MII_MGMT_CONTROL 0xa02c
20 #define MII_MGMT_STATUS 0xa030
21 #define MII_MGMT_INDICATORS 0xa034
22 #define INTERFACE_CONTROL 0xa038
23 #define STATION_ADDR0 0xa040
24 #define STATION_ADDR1 0xa044
25
26 #define RGMII_REG_0 0x27e0
27 #define ICM_CONFIG0_REG_0 0x2c00
28 #define ICM_CONFIG2_REG_0 0x2c08
29 #define ECM_CONFIG0_REG_0 0x2d00
30
31 /* Register fields */
32 #define SOFT_RESET BIT(31)
33 #define TX_EN BIT(0)
34 #define RX_EN BIT(2)
35 #define PAD_CRC BIT(2)
36 #define CRC_EN BIT(1)
37 #define FULL_DUPLEX BIT(0)
38
39 #define INTF_MODE_POS 8
40 #define INTF_MODE_LEN 2
41 #define HD_MODE_POS 25
42 #define HD_MODE_LEN 2
43 #define CFG_MACMODE_POS 18
44 #define CFG_MACMODE_LEN 2
45 #define CFG_WAITASYNCRD_POS 0
46 #define CFG_WAITASYNCRD_LEN 16
47 #define CFG_SPEED_125_POS 24
48 #define CFG_WFIFOFULLTHR_POS 0
49 #define CFG_WFIFOFULLTHR_LEN 7
50 #define MGMT_CLOCK_SEL_POS 0
51 #define MGMT_CLOCK_SEL_LEN 3
52 #define PHY_ADDR_POS 8
53 #define PHY_ADDR_LEN 5
54 #define REG_ADDR_POS 0
55 #define REG_ADDR_LEN 5
56 #define MII_MGMT_BUSY BIT(0)
57 #define MII_READ_CYCLE BIT(0)
58 #define CFG_WAITASYNCRD_EN BIT(16)
59
xgene_set_reg_bits(u32 * var,int pos,int len,u32 val)60 static inline void xgene_set_reg_bits(u32 *var, int pos, int len, u32 val)
61 {
62 u32 mask = GENMASK(pos + len, pos);
63
64 *var &= ~mask;
65 *var |= ((val << pos) & mask);
66 }
67
xgene_get_reg_bits(u32 var,int pos,int len)68 static inline u32 xgene_get_reg_bits(u32 var, int pos, int len)
69 {
70 u32 mask = GENMASK(pos + len, pos);
71
72 return (var & mask) >> pos;
73 }
74
75 #define SET_REG_BITS(var, field, val) \
76 xgene_set_reg_bits(var, field ## _POS, field ## _LEN, val)
77
78 #define SET_REG_BIT(var, field, val) \
79 xgene_set_reg_bits(var, field ## _POS, 1, val)
80
81 #define GET_REG_BITS(var, field) \
82 xgene_get_reg_bits(var, field ## _POS, field ## _LEN)
83
84 #define GET_REG_BIT(var, field) ((var) & (field))
85
86 struct xge_pdata;
87
88 void xge_mac_reset(struct xge_pdata *pdata);
89 void xge_mac_set_speed(struct xge_pdata *pdata);
90 void xge_mac_enable(struct xge_pdata *pdata);
91 void xge_mac_disable(struct xge_pdata *pdata);
92 void xge_mac_init(struct xge_pdata *pdata);
93 void xge_mac_set_station_addr(struct xge_pdata *pdata);
94
95 #endif /* __XGENE_ENET_V2_MAC_H__ */
96