1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd.
4  * Copyright (C) 2019, Theobroma Systems Design und Consulting GmbH
5  */
6 
7 #ifndef PLATFORM_CONFIG_H
8 #define PLATFORM_CONFIG_H
9 
10 #include <mm/generic_ram_layout.h>
11 
12 /* Make stacks aligned to data cache line length */
13 #define STACK_ALIGNMENT		64
14 
15 #define SIZE_K(n)		((n) * 1024)
16 #define SIZE_M(n)		((n) * 1024 * 1024)
17 
18 #if defined(PLATFORM_FLAVOR_rk322x)
19 
20 #define GIC_BASE		0x32010000
21 #define GIC_SIZE		SIZE_K(64)
22 #define GICD_BASE		(GIC_BASE + 0x1000)
23 #define GICC_BASE		(GIC_BASE + 0x2000)
24 
25 #define SGRF_BASE		0x10140000
26 #define SGRF_SIZE		SIZE_K(64)
27 
28 #define DDRSGRF_BASE		0x10150000
29 #define DDRSGRF_SIZE		SIZE_K(64)
30 
31 #define GRF_BASE		0x11000000
32 #define GRF_SIZE		SIZE_K(64)
33 
34 #define UART2_BASE		0x11030000
35 #define UART2_SIZE		SIZE_K(64)
36 
37 #define CRU_BASE		0x110e0000
38 #define CRU_SIZE		SIZE_K(64)
39 
40 /* Internal SRAM */
41 #define ISRAM_BASE		0x10080000
42 #define ISRAM_SIZE		SIZE_K(8)
43 
44 #elif defined(PLATFORM_FLAVOR_rk3399)
45 
46 #define MMIO_BASE		0xF8000000
47 
48 #define GIC_BASE		(MMIO_BASE + 0x06E00000)
49 #define GIC_SIZE		SIZE_M(2)
50 #define GICC_BASE		(MMIO_BASE + 0x07F00000)
51 #define GICD_BASE		GIC_BASE
52 #define GICR_BASE		(GIC_BASE + SIZE_M(1))
53 
54 #define UART0_BASE		(MMIO_BASE + 0x07180000)
55 #define UART0_SIZE		SIZE_K(64)
56 
57 #define UART1_BASE		(MMIO_BASE + 0x07190000)
58 #define UART1_SIZE		SIZE_K(64)
59 
60 #define UART2_BASE		(MMIO_BASE + 0x071A0000)
61 #define UART2_SIZE		SIZE_K(64)
62 
63 #define UART3_BASE		(MMIO_BASE + 0x071B0000)
64 #define UART3_SIZE		SIZE_K(64)
65 
66 #define SGRF_BASE		(MMIO_BASE + 0x07330000)
67 #define SGRF_SIZE		SIZE_K(64)
68 
69 #elif defined(PLATFORM_FLAVOR_px30)
70 
71 #define GIC_BASE		0xff130000
72 #define GIC_SIZE		SIZE_K(64)
73 #define GICD_BASE		(GIC_BASE + 0x1000)
74 #define GICC_BASE		(GIC_BASE + 0x2000)
75 
76 #define UART1_BASE		0xff158000
77 #define UART1_SIZE		SIZE_K(64)
78 
79 #define UART2_BASE		0xff160000
80 #define UART2_SIZE		SIZE_K(64)
81 
82 #define UART5_BASE		0xff178000
83 #define UART5_SIZE		SIZE_K(64)
84 
85 #define FIREWALL_DDR_BASE	0xff534000
86 #define FIREWALL_DDR_SIZE	SIZE_K(16)
87 
88 #else
89 #error "Unknown platform flavor"
90 #endif
91 
92 #ifdef CFG_WITH_LPAE
93 #define MAX_XLAT_TABLES		5
94 #endif
95 
96 #endif
97