1 /** 2 ****************************************************************************** 3 * @file stm32f7xx_ll_fmc.h 4 * @author MCD Application Team 5 * @version V1.0.1 6 * @date 25-June-2015 7 * @brief Header file of FMC HAL module. 8 ****************************************************************************** 9 * @attention 10 * 11 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 12 * 13 * Redistribution and use in source and binary forms, with or without modification, 14 * are permitted provided that the following conditions are met: 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright notice, 18 * this list of conditions and the following disclaimer in the documentation 19 * and/or other materials provided with the distribution. 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 ****************************************************************************** 36 */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 #ifndef __STM32F7xx_LL_FMC_H 40 #define __STM32F7xx_LL_FMC_H 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32f7xx_hal_def.h" 48 49 /** @addtogroup STM32F7xx_HAL_Driver 50 * @{ 51 */ 52 53 /** @addtogroup FMC_LL 54 * @{ 55 */ 56 57 /** @addtogroup FMC_LL_Private_Macros 58 * @{ 59 */ 60 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ 61 ((BANK) == FMC_NORSRAM_BANK2) || \ 62 ((BANK) == FMC_NORSRAM_BANK3) || \ 63 ((BANK) == FMC_NORSRAM_BANK4)) 64 65 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ 66 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) 67 68 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ 69 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ 70 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) 71 72 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ 73 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ 74 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) 75 76 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ 77 ((__MODE__) == FMC_ACCESS_MODE_B) || \ 78 ((__MODE__) == FMC_ACCESS_MODE_C) || \ 79 ((__MODE__) == FMC_ACCESS_MODE_D)) 80 81 #define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3) 82 83 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ 84 ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE)) 85 86 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \ 87 ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16)) 88 89 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ 90 ((STATE) == FMC_NAND_ECC_ENABLE)) 91 92 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ 93 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ 94 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ 95 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ 96 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ 97 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) 98 99 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ 100 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ 101 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) 102 103 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ 104 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) 105 106 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ 107 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ 108 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) 109 110 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ 111 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) 112 113 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ 114 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ 115 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) 116 117 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ 118 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ 119 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ 120 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ 121 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ 122 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ 123 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) 124 125 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ 126 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ 127 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) 128 129 /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time 130 * @{ 131 */ 132 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255) 133 /** 134 * @} 135 */ 136 137 /** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time 138 * @{ 139 */ 140 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) 141 /** 142 * @} 143 */ 144 145 /** @defgroup FMC_Setup_Time FMC Setup Time 146 * @{ 147 */ 148 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254) 149 /** 150 * @} 151 */ 152 153 /** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time 154 * @{ 155 */ 156 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254) 157 /** 158 * @} 159 */ 160 161 /** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time 162 * @{ 163 */ 164 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254) 165 /** 166 * @} 167 */ 168 169 /** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time 170 * @{ 171 */ 172 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254) 173 /** 174 * @} 175 */ 176 177 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ 178 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) 179 180 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ 181 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) 182 183 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ 184 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) 185 186 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ 187 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) 188 189 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ 190 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) 191 192 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ 193 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) 194 195 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ 196 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) 197 198 /** @defgroup FMC_Data_Latency FMC Data Latency 199 * @{ 200 */ 201 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) 202 /** 203 * @} 204 */ 205 206 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ 207 ((__BURST__) == FMC_WRITE_BURST_ENABLE)) 208 209 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ 210 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) 211 212 213 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time 214 * @{ 215 */ 216 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) 217 /** 218 * @} 219 */ 220 221 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time 222 * @{ 223 */ 224 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) 225 /** 226 * @} 227 */ 228 229 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time 230 * @{ 231 */ 232 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) 233 /** 234 * @} 235 */ 236 237 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration 238 * @{ 239 */ 240 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) 241 /** 242 * @} 243 */ 244 245 /** @defgroup FMC_CLK_Division FMC CLK Division 246 * @{ 247 */ 248 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16)) 249 /** 250 * @} 251 */ 252 253 /** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay 254 * @{ 255 */ 256 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 257 /** 258 * @} 259 */ 260 261 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay 262 * @{ 263 */ 264 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 265 /** 266 * @} 267 */ 268 269 /** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time 270 * @{ 271 */ 272 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) 273 /** 274 * @} 275 */ 276 277 /** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay 278 * @{ 279 */ 280 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 281 /** 282 * @} 283 */ 284 285 /** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time 286 * @{ 287 */ 288 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16)) 289 /** 290 * @} 291 */ 292 293 /** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay 294 * @{ 295 */ 296 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 297 /** 298 * @} 299 */ 300 301 /** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay 302 * @{ 303 */ 304 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16)) 305 /** 306 * @} 307 */ 308 309 /** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number 310 * @{ 311 */ 312 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16)) 313 /** 314 * @} 315 */ 316 317 /** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition 318 * @{ 319 */ 320 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191) 321 /** 322 * @} 323 */ 324 325 /** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate 326 * @{ 327 */ 328 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191) 329 /** 330 * @} 331 */ 332 333 /** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance 334 * @{ 335 */ 336 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) 337 /** 338 * @} 339 */ 340 341 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance 342 * @{ 343 */ 344 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) 345 /** 346 * @} 347 */ 348 349 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance 350 * @{ 351 */ 352 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) 353 /** 354 * @} 355 */ 356 357 /** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance 358 * @{ 359 */ 360 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) 361 /** 362 * @} 363 */ 364 365 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ 366 ((BANK) == FMC_SDRAM_BANK2)) 367 368 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ 369 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ 370 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ 371 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) 372 373 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ 374 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ 375 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) 376 377 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ 378 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) 379 380 381 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ 382 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ 383 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) 384 385 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ 386 ((__SIZE__) == FMC_PAGE_SIZE_128) || \ 387 ((__SIZE__) == FMC_PAGE_SIZE_256) || \ 388 ((__SIZE__) == FMC_PAGE_SIZE_1024)) 389 390 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ 391 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) 392 /** 393 * @} 394 */ 395 396 /* Exported typedef ----------------------------------------------------------*/ 397 /** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types 398 * @{ 399 */ 400 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef 401 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef 402 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef 403 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef 404 405 #define FMC_NORSRAM_DEVICE FMC_Bank1 406 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E 407 #define FMC_NAND_DEVICE FMC_Bank3 408 #define FMC_SDRAM_DEVICE FMC_Bank5_6 409 410 /** 411 * @brief FMC NORSRAM Configuration Structure definition 412 */ 413 typedef struct { 414 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. 415 This parameter can be a value of @ref FMC_NORSRAM_Bank */ 416 417 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are 418 multiplexed on the data bus or not. 419 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ 420 421 uint32_t MemoryType; /*!< Specifies the type of external memory attached to 422 the corresponding memory device. 423 This parameter can be a value of @ref FMC_Memory_Type */ 424 425 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 426 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ 427 428 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, 429 valid only with synchronous burst Flash memories. 430 This parameter can be a value of @ref FMC_Burst_Access_Mode */ 431 432 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing 433 the Flash memory in burst mode. 434 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ 435 436 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one 437 clock cycle before the wait state or during the wait state, 438 valid only when accessing memories in burst mode. 439 This parameter can be a value of @ref FMC_Wait_Timing */ 440 441 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. 442 This parameter can be a value of @ref FMC_Write_Operation */ 443 444 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait 445 signal, valid for Flash memory access in burst mode. 446 This parameter can be a value of @ref FMC_Wait_Signal */ 447 448 uint32_t ExtendedMode; /*!< Enables or disables the extended mode. 449 This parameter can be a value of @ref FMC_Extended_Mode */ 450 451 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, 452 valid only with asynchronous Flash memories. 453 This parameter can be a value of @ref FMC_AsynchronousWait */ 454 455 uint32_t WriteBurst; /*!< Enables or disables the write burst operation. 456 This parameter can be a value of @ref FMC_Write_Burst */ 457 458 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. 459 This parameter is only enabled through the FMC_BCR1 register, and don't care 460 through FMC_BCR2..4 registers. 461 This parameter can be a value of @ref FMC_Continous_Clock */ 462 463 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. 464 This parameter is only enabled through the FMC_BCR1 register, and don't care 465 through FMC_BCR2..4 registers. 466 This parameter can be a value of @ref FMC_Write_FIFO */ 467 468 uint32_t PageSize; /*!< Specifies the memory page size. 469 This parameter can be a value of @ref FMC_Page_Size */ 470 471 } FMC_NORSRAM_InitTypeDef; 472 473 /** 474 * @brief FMC NORSRAM Timing parameters structure definition 475 */ 476 typedef struct { 477 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure 478 the duration of the address setup time. 479 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 480 @note This parameter is not used with synchronous NOR Flash memories. */ 481 482 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure 483 the duration of the address hold time. 484 This parameter can be a value between Min_Data = 1 and Max_Data = 15. 485 @note This parameter is not used with synchronous NOR Flash memories. */ 486 487 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure 488 the duration of the data setup time. 489 This parameter can be a value between Min_Data = 1 and Max_Data = 255. 490 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 491 NOR Flash memories. */ 492 493 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure 494 the duration of the bus turnaround. 495 This parameter can be a value between Min_Data = 0 and Max_Data = 15. 496 @note This parameter is only used for multiplexed NOR Flash memories. */ 497 498 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of 499 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. 500 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 501 accesses. */ 502 503 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue 504 to the memory before getting the first data. 505 The parameter value depends on the memory type as shown below: 506 - It must be set to 0 in case of a CRAM 507 - It is don't care in asynchronous NOR, SRAM or ROM accesses 508 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories 509 with synchronous burst mode enable */ 510 511 uint32_t AccessMode; /*!< Specifies the asynchronous access mode. 512 This parameter can be a value of @ref FMC_Access_Mode */ 513 } FMC_NORSRAM_TimingTypeDef; 514 515 /** 516 * @brief FMC NAND Configuration Structure definition 517 */ 518 typedef struct { 519 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. 520 This parameter can be a value of @ref FMC_NAND_Bank */ 521 522 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. 523 This parameter can be any value of @ref FMC_Wait_feature */ 524 525 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. 526 This parameter can be any value of @ref FMC_NAND_Data_Width */ 527 528 uint32_t EccComputation; /*!< Enables or disables the ECC computation. 529 This parameter can be any value of @ref FMC_ECC */ 530 531 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. 532 This parameter can be any value of @ref FMC_ECC_Page_Size */ 533 534 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the 535 delay between CLE low and RE low. 536 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 537 538 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the 539 delay between ALE low and RE low. 540 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ 541 } FMC_NAND_InitTypeDef; 542 543 /** 544 * @brief FMC NAND Timing parameters structure definition 545 */ 546 typedef struct { 547 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before 548 the command assertion for NAND-Flash read or write access 549 to common/Attribute or I/O memory space (depending on 550 the memory space timing to be configured). 551 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ 552 553 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the 554 command for NAND-Flash read or write access to 555 common/Attribute or I/O memory space (depending on the 556 memory space timing to be configured). 557 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 558 559 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address 560 (and data for write access) after the command de-assertion 561 for NAND-Flash read or write access to common/Attribute 562 or I/O memory space (depending on the memory space timing 563 to be configured). 564 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 565 566 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the 567 data bus is kept in HiZ after the start of a NAND-Flash 568 write access to common/Attribute or I/O memory space (depending 569 on the memory space timing to be configured). 570 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ 571 } FMC_NAND_PCC_TimingTypeDef; 572 573 /** 574 * @brief FMC SDRAM Configuration Structure definition 575 */ 576 typedef struct { 577 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. 578 This parameter can be a value of @ref FMC_SDRAM_Bank */ 579 580 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. 581 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ 582 583 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. 584 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ 585 586 uint32_t MemoryDataWidth; /*!< Defines the memory device width. 587 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ 588 589 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. 590 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ 591 592 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. 593 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ 594 595 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. 596 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ 597 598 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow 599 to disable the clock before changing frequency. 600 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ 601 602 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read 603 commands during the CAS latency and stores data in the Read FIFO. 604 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ 605 606 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. 607 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ 608 } FMC_SDRAM_InitTypeDef; 609 610 /** 611 * @brief FMC SDRAM Timing parameters structure definition 612 */ 613 typedef struct { 614 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and 615 an active or Refresh command in number of memory clock cycles. 616 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 617 618 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to 619 issuing the Activate command in number of memory clock cycles. 620 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 621 622 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock 623 cycles. 624 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 625 626 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command 627 and the delay between two consecutive Refresh commands in number of 628 memory clock cycles. 629 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 630 631 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. 632 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 633 634 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command 635 in number of memory clock cycles. 636 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 637 638 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write 639 command in number of memory clock cycles. 640 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 641 } FMC_SDRAM_TimingTypeDef; 642 643 /** 644 * @brief SDRAM command parameters structure definition 645 */ 646 typedef struct { 647 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. 648 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ 649 650 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. 651 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ 652 653 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued 654 in auto refresh mode. 655 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ 656 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ 657 } FMC_SDRAM_CommandTypeDef; 658 /** 659 * @} 660 */ 661 662 /* Exported constants --------------------------------------------------------*/ 663 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants 664 * @{ 665 */ 666 667 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller 668 * @{ 669 */ 670 671 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank 672 * @{ 673 */ 674 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) 675 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) 676 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) 677 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) 678 /** 679 * @} 680 */ 681 682 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing 683 * @{ 684 */ 685 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) 686 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) 687 /** 688 * @} 689 */ 690 691 /** @defgroup FMC_Memory_Type FMC Memory Type 692 * @{ 693 */ 694 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) 695 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) 696 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) 697 /** 698 * @} 699 */ 700 701 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width 702 * @{ 703 */ 704 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) 705 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) 706 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) 707 /** 708 * @} 709 */ 710 711 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access 712 * @{ 713 */ 714 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) 715 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) 716 /** 717 * @} 718 */ 719 720 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode 721 * @{ 722 */ 723 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) 724 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) 725 /** 726 * @} 727 */ 728 729 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity 730 * @{ 731 */ 732 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) 733 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) 734 /** 735 * @} 736 */ 737 738 /** @defgroup FMC_Wait_Timing FMC Wait Timing 739 * @{ 740 */ 741 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) 742 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) 743 /** 744 * @} 745 */ 746 747 /** @defgroup FMC_Write_Operation FMC Write Operation 748 * @{ 749 */ 750 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) 751 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) 752 /** 753 * @} 754 */ 755 756 /** @defgroup FMC_Wait_Signal FMC Wait Signal 757 * @{ 758 */ 759 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) 760 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) 761 /** 762 * @} 763 */ 764 765 /** @defgroup FMC_Extended_Mode FMC Extended Mode 766 * @{ 767 */ 768 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) 769 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) 770 /** 771 * @} 772 */ 773 774 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait 775 * @{ 776 */ 777 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) 778 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) 779 /** 780 * @} 781 */ 782 783 /** @defgroup FMC_Page_Size FMC Page Size 784 * @{ 785 */ 786 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) 787 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) 788 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) 789 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) 790 /** 791 * @} 792 */ 793 794 /** @defgroup FMC_Write_Burst FMC Write Burst 795 * @{ 796 */ 797 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) 798 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) 799 /** 800 * @} 801 */ 802 803 /** @defgroup FMC_Continous_Clock FMC Continuous Clock 804 * @{ 805 */ 806 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) 807 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) 808 /** 809 * @} 810 */ 811 812 /** @defgroup FMC_Write_FIFO FMC Write FIFO 813 * @{ 814 */ 815 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000) 816 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS) 817 /** 818 * @} 819 */ 820 821 /** @defgroup FMC_Access_Mode FMC Access Mode 822 * @{ 823 */ 824 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) 825 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) 826 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) 827 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) 828 /** 829 * @} 830 */ 831 832 /** 833 * @} 834 */ 835 836 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller 837 * @{ 838 */ 839 /** @defgroup FMC_NAND_Bank FMC NAND Bank 840 * @{ 841 */ 842 #define FMC_NAND_BANK3 ((uint32_t)0x00000100) 843 /** 844 * @} 845 */ 846 847 /** @defgroup FMC_Wait_feature FMC Wait feature 848 * @{ 849 */ 850 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) 851 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) 852 /** 853 * @} 854 */ 855 856 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type 857 * @{ 858 */ 859 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) 860 /** 861 * @} 862 */ 863 864 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width 865 * @{ 866 */ 867 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) 868 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) 869 /** 870 * @} 871 */ 872 873 /** @defgroup FMC_ECC FMC ECC 874 * @{ 875 */ 876 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) 877 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) 878 /** 879 * @} 880 */ 881 882 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size 883 * @{ 884 */ 885 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) 886 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) 887 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) 888 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) 889 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) 890 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) 891 /** 892 * @} 893 */ 894 895 /** 896 * @} 897 */ 898 899 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller 900 * @{ 901 */ 902 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank 903 * @{ 904 */ 905 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) 906 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) 907 /** 908 * @} 909 */ 910 911 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number 912 * @{ 913 */ 914 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) 915 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) 916 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) 917 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) 918 /** 919 * @} 920 */ 921 922 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number 923 * @{ 924 */ 925 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) 926 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) 927 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) 928 /** 929 * @} 930 */ 931 932 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width 933 * @{ 934 */ 935 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) 936 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) 937 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) 938 /** 939 * @} 940 */ 941 942 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number 943 * @{ 944 */ 945 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) 946 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) 947 /** 948 * @} 949 */ 950 951 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency 952 * @{ 953 */ 954 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) 955 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) 956 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) 957 /** 958 * @} 959 */ 960 961 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection 962 * @{ 963 */ 964 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) 965 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) 966 /** 967 * @} 968 */ 969 970 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period 971 * @{ 972 */ 973 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) 974 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) 975 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) 976 /** 977 * @} 978 */ 979 980 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst 981 * @{ 982 */ 983 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) 984 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) 985 /** 986 * @} 987 */ 988 989 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay 990 * @{ 991 */ 992 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) 993 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) 994 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) 995 /** 996 * @} 997 */ 998 999 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode 1000 * @{ 1001 */ 1002 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) 1003 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) 1004 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) 1005 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) 1006 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) 1007 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) 1008 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) 1009 /** 1010 * @} 1011 */ 1012 1013 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target 1014 * @{ 1015 */ 1016 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 1017 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 1018 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) 1019 /** 1020 * @} 1021 */ 1022 1023 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status 1024 * @{ 1025 */ 1026 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) 1027 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 1028 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 1029 /** 1030 * @} 1031 */ 1032 1033 /** 1034 * @} 1035 */ 1036 1037 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition 1038 * @{ 1039 */ 1040 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) 1041 #define FMC_IT_LEVEL ((uint32_t)0x00000010) 1042 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) 1043 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) 1044 /** 1045 * @} 1046 */ 1047 1048 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition 1049 * @{ 1050 */ 1051 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) 1052 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002) 1053 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) 1054 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040) 1055 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE 1056 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY 1057 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE 1058 /** 1059 * @} 1060 */ 1061 /** 1062 * @} 1063 */ 1064 1065 /** 1066 * @} 1067 */ 1068 1069 /* Private macro -------------------------------------------------------------*/ 1070 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros 1071 * @{ 1072 */ 1073 1074 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros 1075 * @brief macros to handle NOR device enable/disable and read/write operations 1076 * @{ 1077 */ 1078 1079 /** 1080 * @brief Enable the NORSRAM device access. 1081 * @param __INSTANCE__: FMC_NORSRAM Instance 1082 * @param __BANK__: FMC_NORSRAM Bank 1083 * @retval None 1084 */ 1085 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) 1086 1087 /** 1088 * @brief Disable the NORSRAM device access. 1089 * @param __INSTANCE__: FMC_NORSRAM Instance 1090 * @param __BANK__: FMC_NORSRAM Bank 1091 * @retval None 1092 */ 1093 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) 1094 1095 /** 1096 * @} 1097 */ 1098 1099 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros 1100 * @brief macros to handle NAND device enable/disable 1101 * @{ 1102 */ 1103 1104 /** 1105 * @brief Enable the NAND device access. 1106 * @param __INSTANCE__: FMC_NAND Instance 1107 * @retval None 1108 */ 1109 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) 1110 1111 /** 1112 * @brief Disable the NAND device access. 1113 * @param __INSTANCE__: FMC_NAND Instance 1114 * @retval None 1115 */ 1116 #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) 1117 1118 /** 1119 * @} 1120 */ 1121 1122 /** @defgroup FMC_Interrupt FMC Interrupt 1123 * @brief macros to handle FMC interrupts 1124 * @{ 1125 */ 1126 1127 /** 1128 * @brief Enable the NAND device interrupt. 1129 * @param __INSTANCE__: FMC_NAND instance 1130 * @param __INTERRUPT__: FMC_NAND interrupt 1131 * This parameter can be any combination of the following values: 1132 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1133 * @arg FMC_IT_LEVEL: Interrupt level. 1134 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1135 * @retval None 1136 */ 1137 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) 1138 1139 /** 1140 * @brief Disable the NAND device interrupt. 1141 * @param __INSTANCE__: FMC_NAND Instance 1142 * @param __INTERRUPT__: FMC_NAND interrupt 1143 * This parameter can be any combination of the following values: 1144 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. 1145 * @arg FMC_IT_LEVEL: Interrupt level. 1146 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. 1147 * @retval None 1148 */ 1149 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) 1150 1151 /** 1152 * @brief Get flag status of the NAND device. 1153 * @param __INSTANCE__: FMC_NAND Instance 1154 * @param __BANK__: FMC_NAND Bank 1155 * @param __FLAG__: FMC_NAND flag 1156 * This parameter can be any combination of the following values: 1157 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1158 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1159 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1160 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1161 * @retval The state of FLAG (SET or RESET). 1162 */ 1163 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) 1164 1165 /** 1166 * @brief Clear flag status of the NAND device. 1167 * @param __INSTANCE__: FMC_NAND Instance 1168 * @param __FLAG__: FMC_NAND flag 1169 * This parameter can be any combination of the following values: 1170 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. 1171 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. 1172 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. 1173 * @arg FMC_FLAG_FEMPT: FIFO empty flag. 1174 * @retval None 1175 */ 1176 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) 1177 1178 /** 1179 * @brief Enable the SDRAM device interrupt. 1180 * @param __INSTANCE__: FMC_SDRAM instance 1181 * @param __INTERRUPT__: FMC_SDRAM interrupt 1182 * This parameter can be any combination of the following values: 1183 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1184 * @retval None 1185 */ 1186 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) 1187 1188 /** 1189 * @brief Disable the SDRAM device interrupt. 1190 * @param __INSTANCE__: FMC_SDRAM instance 1191 * @param __INTERRUPT__: FMC_SDRAM interrupt 1192 * This parameter can be any combination of the following values: 1193 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error 1194 * @retval None 1195 */ 1196 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) 1197 1198 /** 1199 * @brief Get flag status of the SDRAM device. 1200 * @param __INSTANCE__: FMC_SDRAM instance 1201 * @param __FLAG__: FMC_SDRAM flag 1202 * This parameter can be any combination of the following values: 1203 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. 1204 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. 1205 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. 1206 * @retval The state of FLAG (SET or RESET). 1207 */ 1208 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) 1209 1210 /** 1211 * @brief Clear flag status of the SDRAM device. 1212 * @param __INSTANCE__: FMC_SDRAM instance 1213 * @param __FLAG__: FMC_SDRAM flag 1214 * This parameter can be any combination of the following values: 1215 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR 1216 * @retval None 1217 */ 1218 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) 1219 /** 1220 * @} 1221 */ 1222 1223 /** 1224 * @} 1225 */ 1226 1227 /* Private functions ---------------------------------------------------------*/ 1228 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions 1229 * @{ 1230 */ 1231 1232 /** @defgroup FMC_LL_NORSRAM NOR SRAM 1233 * @{ 1234 */ 1235 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions 1236 * @{ 1237 */ 1238 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); 1239 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); 1240 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); 1241 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); 1242 /** 1243 * @} 1244 */ 1245 1246 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions 1247 * @{ 1248 */ 1249 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1250 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); 1251 /** 1252 * @} 1253 */ 1254 /** 1255 * @} 1256 */ 1257 1258 /** @defgroup FMC_LL_NAND NAND 1259 * @{ 1260 */ 1261 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions 1262 * @{ 1263 */ 1264 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); 1265 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1266 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); 1267 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); 1268 /** 1269 * @} 1270 */ 1271 1272 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions 1273 * @{ 1274 */ 1275 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1276 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); 1277 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); 1278 /** 1279 * @} 1280 */ 1281 1282 /** @defgroup FMC_LL_SDRAM SDRAM 1283 * @{ 1284 */ 1285 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions 1286 * @{ 1287 */ 1288 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); 1289 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); 1290 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1291 1292 /** 1293 * @} 1294 */ 1295 1296 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions 1297 * @{ 1298 */ 1299 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1300 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1301 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); 1302 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); 1303 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); 1304 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); 1305 /** 1306 * @} 1307 */ 1308 1309 /** 1310 * @} 1311 */ 1312 1313 /** 1314 * @} 1315 */ 1316 1317 /** 1318 * @} 1319 */ 1320 1321 /** 1322 * @} 1323 */ 1324 #ifdef __cplusplus 1325 } 1326 #endif 1327 1328 #endif /* __STM32F7xx_LL_FMC_H */ 1329 1330 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1331