1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_fmc.c
4 * @author MCD Application Team
5 * @version V1.0.1
6 * @date 25-June-2015
7 * @brief FMC Low Layer HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
11 * + Initialization/de-initialization functions
12 * + Peripheral Control functions
13 * + Peripheral State functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### FMC peripheral features #####
18 ==============================================================================
19 [..] The Flexible memory controller (FMC) includes three memory controllers:
20 (+) The NOR/PSRAM memory controller
21 (+) The NAND memory controller
22 (+) The Synchronous DRAM (SDRAM) controller
23
24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
26 (+) to translate AHB transactions into the appropriate external device protocol
27 (+) to meet the access time requirements of the external memory devices
28
29 [..] All external memories share the addresses, data and control signals with the controller.
30 Each external device is accessed by means of a unique Chip Select. The FMC performs
31 only one access at a time to an external device.
32 The main features of the FMC controller are the following:
33 (+) Interface with static-memory mapped devices including:
34 (++) Static random access memory (SRAM)
35 (++) Read-only memory (ROM)
36 (++) NOR Flash memory/OneNAND Flash memory
37 (++) PSRAM (4 memory banks)
38 (++) 16-bit PC Card compatible devices
39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
40 data
41 (+) Interface with synchronous DRAM (SDRAM) memories
42 (+) Independent Chip Select control for each memory bank
43 (+) Independent configuration for each memory bank
44
45 @endverbatim
46 ******************************************************************************
47 * @attention
48 *
49 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
50 *
51 * Redistribution and use in source and binary forms, with or without modification,
52 * are permitted provided that the following conditions are met:
53 * 1. Redistributions of source code must retain the above copyright notice,
54 * this list of conditions and the following disclaimer.
55 * 2. Redistributions in binary form must reproduce the above copyright notice,
56 * this list of conditions and the following disclaimer in the documentation
57 * and/or other materials provided with the distribution.
58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
59 * may be used to endorse or promote products derived from this software
60 * without specific prior written permission.
61 *
62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
72 *
73 ******************************************************************************
74 */
75
76 /* Includes ------------------------------------------------------------------*/
77 #include "stm32f7xx_hal.h"
78
79 /** @addtogroup STM32F7xx_HAL_Driver
80 * @{
81 */
82
83 /** @defgroup FMC_LL FMC Low Layer
84 * @brief FMC driver modules
85 * @{
86 */
87
88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
89
90 /* Private typedef -----------------------------------------------------------*/
91 /* Private define ------------------------------------------------------------*/
92 /* Private macro -------------------------------------------------------------*/
93 /* Private variables ---------------------------------------------------------*/
94 /* Private function prototypes -----------------------------------------------*/
95 /* Exported functions --------------------------------------------------------*/
96
97 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
98 * @{
99 */
100
101 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions
102 * @brief NORSRAM Controller functions
103 *
104 @verbatim
105 ==============================================================================
106 ##### How to use NORSRAM device driver #####
107 ==============================================================================
108
109 [..]
110 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
111 to run the NORSRAM external devices.
112
113 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
114 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
115 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
116 (+) FMC NORSRAM bank extended timing configuration using the function
117 FMC_NORSRAM_Extended_Timing_Init()
118 (+) FMC NORSRAM bank enable/disable write operation using the functions
119 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
120
121
122 @endverbatim
123 * @{
124 */
125
126 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions
127 * @brief Initialization and Configuration functions
128 *
129 @verbatim
130 ==============================================================================
131 ##### Initialization and de_initialization functions #####
132 ==============================================================================
133 [..]
134 This section provides functions allowing to:
135 (+) Initialize and configure the FMC NORSRAM interface
136 (+) De-initialize the FMC NORSRAM interface
137 (+) Configure the FMC clock and associated GPIOs
138
139 @endverbatim
140 * @{
141 */
142
143 /**
144 * @brief Initialize the FMC_NORSRAM device according to the specified
145 * control parameters in the FMC_NORSRAM_InitTypeDef
146 * @param Device: Pointer to NORSRAM device instance
147 * @param Init: Pointer to NORSRAM Initialization structure
148 * @retval HAL status
149 */
FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_InitTypeDef * Init)150 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
151 {
152 uint32_t tmpr = 0;
153
154 /* Check the parameters */
155 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
156 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
157 assert_param(IS_FMC_MUX(Init->DataAddressMux));
158 assert_param(IS_FMC_MEMORY(Init->MemoryType));
159 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
160 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
161 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
162 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
163 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
164 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
165 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
166 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
167 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
168 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
169 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
170 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
171
172 /* Get the BTCR register value */
173 tmpr = Device->BTCR[Init->NSBank];
174
175 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN,
176 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
177 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
178 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
179 FMC_BCR1_WAITPOL | FMC_BCR1_CPSIZE | FMC_BCR1_WAITCFG | \
180 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
181 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | FMC_BCR1_WFDIS));
182
183 /* Set NORSRAM device control parameters */
184 tmpr |= (uint32_t)(Init->DataAddressMux |\
185 Init->MemoryType |\
186 Init->MemoryDataWidth |\
187 Init->BurstAccessMode |\
188 Init->WaitSignalPolarity |\
189 Init->WaitSignalActive |\
190 Init->WriteOperation |\
191 Init->WaitSignal |\
192 Init->ExtendedMode |\
193 Init->AsynchronousWait |\
194 Init->WriteBurst |\
195 Init->ContinuousClock |\
196 Init->PageSize |\
197 Init->WriteFifo);
198
199 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) {
200 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
201 }
202
203 Device->BTCR[Init->NSBank] = tmpr;
204
205 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
206 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) {
207 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE;
208 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\
209 Init->ContinuousClock);
210 }
211 if (Init->NSBank != FMC_NORSRAM_BANK1) {
212 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
213 }
214
215 return HAL_OK;
216 }
217
218
219 /**
220 * @brief DeInitialize the FMC_NORSRAM peripheral
221 * @param Device: Pointer to NORSRAM device instance
222 * @param ExDevice: Pointer to NORSRAM extended mode device instance
223 * @param Bank: NORSRAM bank number
224 * @retval HAL status
225 */
FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_EXTENDED_TypeDef * ExDevice,uint32_t Bank)226 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
227 {
228 /* Check the parameters */
229 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
230 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
231 assert_param(IS_FMC_NORSRAM_BANK(Bank));
232
233 /* Disable the FMC_NORSRAM device */
234 __FMC_NORSRAM_DISABLE(Device, Bank);
235
236 /* De-initialize the FMC_NORSRAM device */
237 /* FMC_NORSRAM_BANK1 */
238 if (Bank == FMC_NORSRAM_BANK1) {
239 Device->BTCR[Bank] = 0x000030DB;
240 }
241 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
242 else {
243 Device->BTCR[Bank] = 0x000030D2;
244 }
245
246 Device->BTCR[Bank + 1] = 0x0FFFFFFF;
247 ExDevice->BWTR[Bank] = 0x0FFFFFFF;
248
249 return HAL_OK;
250 }
251
252
253 /**
254 * @brief Initialize the FMC_NORSRAM Timing according to the specified
255 * parameters in the FMC_NORSRAM_TimingTypeDef
256 * @param Device: Pointer to NORSRAM device instance
257 * @param Timing: Pointer to NORSRAM Timing structure
258 * @param Bank: NORSRAM bank number
259 * @retval HAL status
260 */
FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank)261 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
262 {
263 uint32_t tmpr = 0;
264
265 /* Check the parameters */
266 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
267 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
268 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
269 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
270 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
271 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
272 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
273 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
274 assert_param(IS_FMC_NORSRAM_BANK(Bank));
275
276 /* Get the BTCR register value */
277 tmpr = Device->BTCR[Bank + 1];
278
279 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
280 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
281 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
282 FMC_BTR1_ACCMOD));
283
284 /* Set FMC_NORSRAM device timing parameters */
285 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
286 ((Timing->AddressHoldTime) << 4) |\
287 ((Timing->DataSetupTime) << 8) |\
288 ((Timing->BusTurnAroundDuration) << 16) |\
289 (((Timing->CLKDivision)-1) << 20) |\
290 (((Timing->DataLatency)-2) << 24) |\
291 (Timing->AccessMode)
292 );
293
294 Device->BTCR[Bank + 1] = tmpr;
295
296 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
297 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) {
298 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20));
299 tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20);
300 Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr;
301 }
302
303 return HAL_OK;
304 }
305
306 /**
307 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
308 * parameters in the FMC_NORSRAM_TimingTypeDef
309 * @param Device: Pointer to NORSRAM device instance
310 * @param Timing: Pointer to NORSRAM Timing structure
311 * @param Bank: NORSRAM bank number
312 * @retval HAL status
313 */
FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef * Device,FMC_NORSRAM_TimingTypeDef * Timing,uint32_t Bank,uint32_t ExtendedMode)314 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
315 {
316 uint32_t tmpr = 0;
317
318 /* Check the parameters */
319 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
320
321 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
322 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) {
323 /* Check the parameters */
324 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
325 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
326 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
327 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
328 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
329 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
330 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
331 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
332 assert_param(IS_FMC_NORSRAM_BANK(Bank));
333
334 /* Get the BWTR register value */
335 tmpr = Device->BWTR[Bank];
336
337 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
338 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
339 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
340
341 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
342 ((Timing->AddressHoldTime) << 4) |\
343 ((Timing->DataSetupTime) << 8) |\
344 ((Timing->BusTurnAroundDuration) << 16) |\
345 (Timing->AccessMode));
346
347 Device->BWTR[Bank] = tmpr;
348 } else {
349 Device->BWTR[Bank] = 0x0FFFFFFF;
350 }
351
352 return HAL_OK;
353 }
354 /**
355 * @}
356 */
357
358 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
359 * @brief management functions
360 *
361 @verbatim
362 ==============================================================================
363 ##### FMC_NORSRAM Control functions #####
364 ==============================================================================
365 [..]
366 This subsection provides a set of functions allowing to control dynamically
367 the FMC NORSRAM interface.
368
369 @endverbatim
370 * @{
371 */
372
373 /**
374 * @brief Enables dynamically FMC_NORSRAM write operation.
375 * @param Device: Pointer to NORSRAM device instance
376 * @param Bank: NORSRAM bank number
377 * @retval HAL status
378 */
FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)379 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
380 {
381 /* Check the parameters */
382 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
383 assert_param(IS_FMC_NORSRAM_BANK(Bank));
384
385 /* Enable write operation */
386 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
387
388 return HAL_OK;
389 }
390
391 /**
392 * @brief Disables dynamically FMC_NORSRAM write operation.
393 * @param Device: Pointer to NORSRAM device instance
394 * @param Bank: NORSRAM bank number
395 * @retval HAL status
396 */
FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef * Device,uint32_t Bank)397 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
398 {
399 /* Check the parameters */
400 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
401 assert_param(IS_FMC_NORSRAM_BANK(Bank));
402
403 /* Disable write operation */
404 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
405
406 return HAL_OK;
407 }
408
409 /**
410 * @}
411 */
412
413 /**
414 * @}
415 */
416
417 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions
418 * @brief NAND Controller functions
419 *
420 @verbatim
421 ==============================================================================
422 ##### How to use NAND device driver #####
423 ==============================================================================
424 [..]
425 This driver contains a set of APIs to interface with the FMC NAND banks in order
426 to run the NAND external devices.
427
428 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
429 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
430 (+) FMC NAND bank common space timing configuration using the function
431 FMC_NAND_CommonSpace_Timing_Init()
432 (+) FMC NAND bank attribute space timing configuration using the function
433 FMC_NAND_AttributeSpace_Timing_Init()
434 (+) FMC NAND bank enable/disable ECC correction feature using the functions
435 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
436 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
437
438 @endverbatim
439 * @{
440 */
441
442 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
443 * @brief Initialization and Configuration functions
444 *
445 @verbatim
446 ==============================================================================
447 ##### Initialization and de_initialization functions #####
448 ==============================================================================
449 [..]
450 This section provides functions allowing to:
451 (+) Initialize and configure the FMC NAND interface
452 (+) De-initialize the FMC NAND interface
453 (+) Configure the FMC clock and associated GPIOs
454
455 @endverbatim
456 * @{
457 */
458
459 /**
460 * @brief Initializes the FMC_NAND device according to the specified
461 * control parameters in the FMC_NAND_HandleTypeDef
462 * @param Device: Pointer to NAND device instance
463 * @param Init: Pointer to NAND Initialization structure
464 * @retval HAL status
465 */
FMC_NAND_Init(FMC_NAND_TypeDef * Device,FMC_NAND_InitTypeDef * Init)466 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
467 {
468 uint32_t tmpr = 0;
469
470 /* Check the parameters */
471 assert_param(IS_FMC_NAND_DEVICE(Device));
472 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
473 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
474 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
475 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
476 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
477 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
478 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
479
480 /* Get the NAND bank 3 register value */
481 tmpr = Device->PCR;
482
483 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
484 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
485 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
486 FMC_PCR_TAR | FMC_PCR_ECCPS));
487 /* Set NAND device control parameters */
488 tmpr |= (uint32_t)(Init->Waitfeature |\
489 FMC_PCR_MEMORY_TYPE_NAND |\
490 Init->MemoryDataWidth |\
491 Init->EccComputation |\
492 Init->ECCPageSize |\
493 ((Init->TCLRSetupTime) << 9) |\
494 ((Init->TARSetupTime) << 13));
495
496 /* NAND bank 3 registers configuration */
497 Device->PCR = tmpr;
498
499 return HAL_OK;
500
501 }
502
503 /**
504 * @brief Initializes the FMC_NAND Common space Timing according to the specified
505 * parameters in the FMC_NAND_PCC_TimingTypeDef
506 * @param Device: Pointer to NAND device instance
507 * @param Timing: Pointer to NAND timing structure
508 * @param Bank: NAND bank number
509 * @retval HAL status
510 */
FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)511 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
512 {
513 uint32_t tmpr = 0;
514
515 /* Check the parameters */
516 assert_param(IS_FMC_NAND_DEVICE(Device));
517 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
518 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
519 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
520 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
521 assert_param(IS_FMC_NAND_BANK(Bank));
522
523 /* Get the NAND bank 3 register value */
524 tmpr = Device->PMEM;
525
526 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
527 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 | FMC_PMEM_MEMHOLD3 | \
528 FMC_PMEM_MEMHIZ3));
529 /* Set FMC_NAND device timing parameters */
530 tmpr |= (uint32_t)(Timing->SetupTime |\
531 ((Timing->WaitSetupTime) << 8) |\
532 ((Timing->HoldSetupTime) << 16) |\
533 ((Timing->HiZSetupTime) << 24)
534 );
535
536 /* NAND bank 3 registers configuration */
537 Device->PMEM = tmpr;
538
539 return HAL_OK;
540 }
541
542 /**
543 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
544 * parameters in the FMC_NAND_PCC_TimingTypeDef
545 * @param Device: Pointer to NAND device instance
546 * @param Timing: Pointer to NAND timing structure
547 * @param Bank: NAND bank number
548 * @retval HAL status
549 */
FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef * Device,FMC_NAND_PCC_TimingTypeDef * Timing,uint32_t Bank)550 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
551 {
552 uint32_t tmpr = 0;
553
554 /* Check the parameters */
555 assert_param(IS_FMC_NAND_DEVICE(Device));
556 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
557 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
558 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
559 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
560 assert_param(IS_FMC_NAND_BANK(Bank));
561
562 /* Get the NAND bank 3 register value */
563 tmpr = Device->PATT;
564
565 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
566 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 | FMC_PATT_ATTHOLD3 | \
567 FMC_PATT_ATTHIZ3));
568 /* Set FMC_NAND device timing parameters */
569 tmpr |= (uint32_t)(Timing->SetupTime |\
570 ((Timing->WaitSetupTime) << 8) |\
571 ((Timing->HoldSetupTime) << 16) |\
572 ((Timing->HiZSetupTime) << 24));
573
574 /* NAND bank 3 registers configuration */
575 Device->PATT = tmpr;
576
577 return HAL_OK;
578 }
579
580 /**
581 * @brief DeInitializes the FMC_NAND device
582 * @param Device: Pointer to NAND device instance
583 * @param Bank: NAND bank number
584 * @retval HAL status
585 */
FMC_NAND_DeInit(FMC_NAND_TypeDef * Device,uint32_t Bank)586 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
587 {
588 /* Check the parameters */
589 assert_param(IS_FMC_NAND_DEVICE(Device));
590 assert_param(IS_FMC_NAND_BANK(Bank));
591
592 /* Disable the NAND Bank */
593 __FMC_NAND_DISABLE(Device);
594
595 /* Set the FMC_NAND_BANK3 registers to their reset values */
596 Device->PCR = 0x00000018;
597 Device->SR = 0x00000040;
598 Device->PMEM = 0xFCFCFCFC;
599 Device->PATT = 0xFCFCFCFC;
600
601 return HAL_OK;
602 }
603
604 /**
605 * @}
606 */
607
608 /** @defgroup HAL_FMC_NAND_Group3 Control functions
609 * @brief management functions
610 *
611 @verbatim
612 ==============================================================================
613 ##### FMC_NAND Control functions #####
614 ==============================================================================
615 [..]
616 This subsection provides a set of functions allowing to control dynamically
617 the FMC NAND interface.
618
619 @endverbatim
620 * @{
621 */
622
623
624 /**
625 * @brief Enables dynamically FMC_NAND ECC feature.
626 * @param Device: Pointer to NAND device instance
627 * @param Bank: NAND bank number
628 * @retval HAL status
629 */
FMC_NAND_ECC_Enable(FMC_NAND_TypeDef * Device,uint32_t Bank)630 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
631 {
632 /* Check the parameters */
633 assert_param(IS_FMC_NAND_DEVICE(Device));
634 assert_param(IS_FMC_NAND_BANK(Bank));
635
636 /* Enable ECC feature */
637 Device->PCR |= FMC_PCR_ECCEN;
638
639 return HAL_OK;
640 }
641
642
643 /**
644 * @brief Disables dynamically FMC_NAND ECC feature.
645 * @param Device: Pointer to NAND device instance
646 * @param Bank: NAND bank number
647 * @retval HAL status
648 */
FMC_NAND_ECC_Disable(FMC_NAND_TypeDef * Device,uint32_t Bank)649 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
650 {
651 /* Check the parameters */
652 assert_param(IS_FMC_NAND_DEVICE(Device));
653 assert_param(IS_FMC_NAND_BANK(Bank));
654
655 /* Disable ECC feature */
656 Device->PCR &= ~FMC_PCR_ECCEN;
657
658 return HAL_OK;
659 }
660
661 /**
662 * @brief Disables dynamically FMC_NAND ECC feature.
663 * @param Device: Pointer to NAND device instance
664 * @param ECCval: Pointer to ECC value
665 * @param Bank: NAND bank number
666 * @param Timeout: Timeout wait value
667 * @retval HAL status
668 */
FMC_NAND_GetECC(FMC_NAND_TypeDef * Device,uint32_t * ECCval,uint32_t Bank,uint32_t Timeout)669 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
670 {
671 uint32_t tickstart = 0;
672
673 /* Check the parameters */
674 assert_param(IS_FMC_NAND_DEVICE(Device));
675 assert_param(IS_FMC_NAND_BANK(Bank));
676
677 /* Get tick */
678 tickstart = HAL_GetTick();
679
680 /* Wait until FIFO is empty */
681 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) {
682 /* Check for the Timeout */
683 if (Timeout != HAL_MAX_DELAY) {
684 if ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) {
685 return HAL_TIMEOUT;
686 }
687 }
688 }
689
690 /* Get the ECCR register value */
691 *ECCval = (uint32_t)Device->ECCR;
692
693 return HAL_OK;
694 }
695
696 /**
697 * @}
698 */
699
700 /**
701 * @}
702 */
703
704 /** @defgroup FMC_LL_SDRAM
705 * @brief SDRAM Controller functions
706 *
707 @verbatim
708 ==============================================================================
709 ##### How to use SDRAM device driver #####
710 ==============================================================================
711 [..]
712 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
713 to run the SDRAM external devices.
714
715 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
716 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
717 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
718 (+) FMC SDRAM bank enable/disable write operation using the functions
719 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
720 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
721
722 @endverbatim
723 * @{
724 */
725
726 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
727 * @brief Initialization and Configuration functions
728 *
729 @verbatim
730 ==============================================================================
731 ##### Initialization and de_initialization functions #####
732 ==============================================================================
733 [..]
734 This section provides functions allowing to:
735 (+) Initialize and configure the FMC SDRAM interface
736 (+) De-initialize the FMC SDRAM interface
737 (+) Configure the FMC clock and associated GPIOs
738
739 @endverbatim
740 * @{
741 */
742
743 /**
744 * @brief Initializes the FMC_SDRAM device according to the specified
745 * control parameters in the FMC_SDRAM_InitTypeDef
746 * @param Device: Pointer to SDRAM device instance
747 * @param Init: Pointer to SDRAM Initialization structure
748 * @retval HAL status
749 */
FMC_SDRAM_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_InitTypeDef * Init)750 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
751 {
752 uint32_t tmpr1 = 0;
753 uint32_t tmpr2 = 0;
754
755 /* Check the parameters */
756 assert_param(IS_FMC_SDRAM_DEVICE(Device));
757 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
758 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
759 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
760 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
761 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
762 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
763 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
764 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
765 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
766 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
767
768 /* Set SDRAM bank configuration parameters */
769 if (Init->SDBank != FMC_SDRAM_BANK2) {
770 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
771
772 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
773 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
774 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
775 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
776
777 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
778 Init->RowBitsNumber |\
779 Init->MemoryDataWidth |\
780 Init->InternalBankNumber |\
781 Init->CASLatency |\
782 Init->WriteProtection |\
783 Init->SDClockPeriod |\
784 Init->ReadBurst |\
785 Init->ReadPipeDelay
786 );
787 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
788 } else { /* FMC_Bank2_SDRAM */
789 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
790
791 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
792 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
793 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
794 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
795
796 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
797 Init->ReadBurst |\
798 Init->ReadPipeDelay);
799
800 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
801
802 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
803 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
804 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
805 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
806
807 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
808 Init->RowBitsNumber |\
809 Init->MemoryDataWidth |\
810 Init->InternalBankNumber |\
811 Init->CASLatency |\
812 Init->WriteProtection);
813
814 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
815 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
816 }
817
818 return HAL_OK;
819 }
820
821 /**
822 * @brief Initializes the FMC_SDRAM device timing according to the specified
823 * parameters in the FMC_SDRAM_TimingTypeDef
824 * @param Device: Pointer to SDRAM device instance
825 * @param Timing: Pointer to SDRAM Timing structure
826 * @param Bank: SDRAM bank number
827 * @retval HAL status
828 */
FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_TimingTypeDef * Timing,uint32_t Bank)829 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
830 {
831 uint32_t tmpr1 = 0;
832 uint32_t tmpr2 = 0;
833
834 /* Check the parameters */
835 assert_param(IS_FMC_SDRAM_DEVICE(Device));
836 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
837 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
838 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
839 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
840 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
841 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
842 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
843 assert_param(IS_FMC_SDRAM_BANK(Bank));
844
845 /* Set SDRAM device timing parameters */
846 if (Bank != FMC_SDRAM_BANK2) {
847 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
848
849 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
850 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
851 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
852 FMC_SDTR1_TRCD));
853
854 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
855 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
856 (((Timing->SelfRefreshTime)-1) << 8) |\
857 (((Timing->RowCycleDelay)-1) << 12) |\
858 (((Timing->WriteRecoveryTime)-1) <<16) |\
859 (((Timing->RPDelay)-1) << 20) |\
860 (((Timing->RCDDelay)-1) << 24));
861 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
862 } else { /* FMC_Bank2_SDRAM */
863 tmpr1 = Device->SDTR[FMC_SDRAM_BANK2];
864
865 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
866 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
867 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
868 FMC_SDTR1_TRCD));
869
870 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\
871 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
872 (((Timing->SelfRefreshTime)-1) << 8) |\
873 (((Timing->WriteRecoveryTime)-1) <<16) |\
874 (((Timing->RCDDelay)-1) << 24));
875
876 tmpr2 = Device->SDTR[FMC_SDRAM_BANK1];
877
878 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
879 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
880 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
881 FMC_SDTR1_TRCD));
882 tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
883 (((Timing->RPDelay)-1) << 20));
884
885 Device->SDTR[FMC_SDRAM_BANK2] = tmpr1;
886 Device->SDTR[FMC_SDRAM_BANK1] = tmpr2;
887 }
888
889 return HAL_OK;
890 }
891
892 /**
893 * @brief DeInitializes the FMC_SDRAM peripheral
894 * @param Device: Pointer to SDRAM device instance
895 * @retval HAL status
896 */
FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef * Device,uint32_t Bank)897 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
898 {
899 /* Check the parameters */
900 assert_param(IS_FMC_SDRAM_DEVICE(Device));
901 assert_param(IS_FMC_SDRAM_BANK(Bank));
902
903 /* De-initialize the SDRAM device */
904 Device->SDCR[Bank] = 0x000002D0;
905 Device->SDTR[Bank] = 0x0FFFFFFF;
906 Device->SDCMR = 0x00000000;
907 Device->SDRTR = 0x00000000;
908 Device->SDSR = 0x00000000;
909
910 return HAL_OK;
911 }
912
913 /**
914 * @}
915 */
916
917 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
918 * @brief management functions
919 *
920 @verbatim
921 ==============================================================================
922 ##### FMC_SDRAM Control functions #####
923 ==============================================================================
924 [..]
925 This subsection provides a set of functions allowing to control dynamically
926 the FMC SDRAM interface.
927
928 @endverbatim
929 * @{
930 */
931
932 /**
933 * @brief Enables dynamically FMC_SDRAM write protection.
934 * @param Device: Pointer to SDRAM device instance
935 * @param Bank: SDRAM bank number
936 * @retval HAL status
937 */
FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)938 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
939 {
940 /* Check the parameters */
941 assert_param(IS_FMC_SDRAM_DEVICE(Device));
942 assert_param(IS_FMC_SDRAM_BANK(Bank));
943
944 /* Enable write protection */
945 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
946
947 return HAL_OK;
948 }
949
950 /**
951 * @brief Disables dynamically FMC_SDRAM write protection.
952 * @param hsdram: FMC_SDRAM handle
953 * @retval HAL status
954 */
FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef * Device,uint32_t Bank)955 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
956 {
957 /* Check the parameters */
958 assert_param(IS_FMC_SDRAM_DEVICE(Device));
959 assert_param(IS_FMC_SDRAM_BANK(Bank));
960
961 /* Disable write protection */
962 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
963
964 return HAL_OK;
965 }
966
967 /**
968 * @brief Send Command to the FMC SDRAM bank
969 * @param Device: Pointer to SDRAM device instance
970 * @param Command: Pointer to SDRAM command structure
971 * @param Timing: Pointer to SDRAM Timing structure
972 * @param Timeout: Timeout wait value
973 * @retval HAL state
974 */
FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef * Device,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)975 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
976 {
977 __IO uint32_t tmpr = 0;
978 uint32_t tickstart = 0;
979
980 /* Check the parameters */
981 assert_param(IS_FMC_SDRAM_DEVICE(Device));
982 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
983 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
984 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
985 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
986
987 /* Set command register */
988 tmpr = (uint32_t)((Command->CommandMode) |\
989 (Command->CommandTarget) |\
990 (((Command->AutoRefreshNumber)-1) << 5) |\
991 ((Command->ModeRegisterDefinition) << 9)
992 );
993
994 Device->SDCMR = tmpr;
995
996 /* Get tick */
997 tickstart = HAL_GetTick();
998
999 /* wait until command is send */
1000 while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) {
1001 /* Check for the Timeout */
1002 if (Timeout != HAL_MAX_DELAY) {
1003 if ((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) {
1004 return HAL_TIMEOUT;
1005 }
1006 }
1007
1008 return HAL_ERROR;
1009 }
1010
1011 return HAL_OK;
1012 }
1013
1014 /**
1015 * @brief Program the SDRAM Memory Refresh rate.
1016 * @param Device: Pointer to SDRAM device instance
1017 * @param RefreshRate: The SDRAM refresh rate value.
1018 * @retval HAL state
1019 */
FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef * Device,uint32_t RefreshRate)1020 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1021 {
1022 /* Check the parameters */
1023 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1024 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1025
1026 /* Set the refresh rate in command register */
1027 Device->SDRTR |= (RefreshRate<<1);
1028
1029 return HAL_OK;
1030 }
1031
1032 /**
1033 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1034 * @param Device: Pointer to SDRAM device instance
1035 * @param AutoRefreshNumber: Specifies the auto Refresh number.
1036 * @retval None
1037 */
FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef * Device,uint32_t AutoRefreshNumber)1038 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1039 {
1040 /* Check the parameters */
1041 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1042 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1043
1044 /* Set the Auto-refresh number in command register */
1045 Device->SDCMR |= (AutoRefreshNumber << 5);
1046
1047 return HAL_OK;
1048 }
1049
1050 /**
1051 * @brief Returns the indicated FMC SDRAM bank mode status.
1052 * @param Device: Pointer to SDRAM device instance
1053 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
1054 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1055 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1056 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1057 * FMC_SDRAM_POWER_DOWN_MODE.
1058 */
FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef * Device,uint32_t Bank)1059 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1060 {
1061 uint32_t tmpreg = 0;
1062
1063 /* Check the parameters */
1064 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1065 assert_param(IS_FMC_SDRAM_BANK(Bank));
1066
1067 /* Get the corresponding bank mode */
1068 if (Bank == FMC_SDRAM_BANK1) {
1069 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1070 } else {
1071 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2);
1072 }
1073
1074 /* Return the mode status */
1075 return tmpreg;
1076 }
1077
1078 /**
1079 * @}
1080 */
1081
1082 /**
1083 * @}
1084 */
1085
1086 /**
1087 * @}
1088 */
1089 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
1090
1091 /**
1092 * @}
1093 */
1094
1095 /**
1096 * @}
1097 */
1098
1099 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1100