1 /* 2 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 /* number of interrupt handlers. increase as required */ 16 #define MAX_INTR_EL3 2 17 /* List all consoles */ 18 #define VERSAL_CONSOLE_ID_pl011 1 19 #define VERSAL_CONSOLE_ID_pl011_0 1 20 #define VERSAL_CONSOLE_ID_pl011_1 2 21 #define VERSAL_CONSOLE_ID_dcc 3 22 23 #define VERSAL_CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 24 25 /* List all supported platforms */ 26 #define VERSAL_PLATFORM_ID_versal_virt 1 27 #define VERSAL_PLATFORM_ID_spp_itr6 2 28 #define VERSAL_PLATFORM_ID_emu_itr6 3 29 #define VERSAL_PLATFORM_ID_silicon 4 30 31 #define VERSAL_PLATFORM_IS(con) (VERSAL_PLATFORM_ID_ ## con == VERSAL_PLATFORM) 32 33 /* Firmware Image Package */ 34 #define VERSAL_PRIMARY_CPU 0 35 36 /******************************************************************************* 37 * memory map related constants 38 ******************************************************************************/ 39 #define DEVICE0_BASE 0xFF000000 40 #define DEVICE0_SIZE 0x00E00000 41 #define DEVICE1_BASE 0xF9000000 42 #define DEVICE1_SIZE 0x00800000 43 44 /******************************************************************************* 45 * IRQ constants 46 ******************************************************************************/ 47 #define VERSAL_IRQ_SEC_PHY_TIMER U(29) 48 49 /******************************************************************************* 50 * CCI-400 related constants 51 ******************************************************************************/ 52 #define PLAT_ARM_CCI_BASE 0xFD000000 53 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 54 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 55 56 /******************************************************************************* 57 * UART related constants 58 ******************************************************************************/ 59 #define VERSAL_UART0_BASE 0xFF000000 60 #define VERSAL_UART1_BASE 0xFF010000 61 62 #if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc) 63 # define VERSAL_UART_BASE VERSAL_UART0_BASE 64 #elif VERSAL_CONSOLE_IS(pl011_1) 65 # define VERSAL_UART_BASE VERSAL_UART1_BASE 66 #else 67 # error "invalid VERSAL_CONSOLE" 68 #endif 69 70 #define PLAT_VERSAL_CRASH_UART_BASE VERSAL_UART_BASE 71 #define PLAT_VERSAL_CRASH_UART_CLK_IN_HZ VERSAL_UART_CLOCK 72 #define VERSAL_CONSOLE_BAUDRATE VERSAL_UART_BAUDRATE 73 74 /******************************************************************************* 75 * Platform related constants 76 ******************************************************************************/ 77 #if VERSAL_PLATFORM_IS(versal_virt) 78 # define PLATFORM_NAME "Versal Virt" 79 # define VERSAL_UART_CLOCK 25000000 80 # define VERSAL_UART_BAUDRATE 115200 81 # define VERSAL_CPU_CLOCK 2720000 82 #elif VERSAL_PLATFORM_IS(silicon) 83 # define PLATFORM_NAME "Versal Silicon" 84 # define VERSAL_UART_CLOCK 100000000 85 # define VERSAL_UART_BAUDRATE 115200 86 # define VERSAL_CPU_CLOCK 100000000 87 #elif VERSAL_PLATFORM_IS(spp_itr6) 88 # define PLATFORM_NAME "SPP ITR6" 89 # define VERSAL_UART_CLOCK 25000000 90 # define VERSAL_UART_BAUDRATE 115200 91 # define VERSAL_CPU_CLOCK 2720000 92 #elif VERSAL_PLATFORM_IS(emu_itr6) 93 # define PLATFORM_NAME "EMU ITR6" 94 # define VERSAL_UART_CLOCK 212000 95 # define VERSAL_UART_BAUDRATE 9600 96 # define VERSAL_CPU_CLOCK 212000 97 #endif 98 99 /* Access control register defines */ 100 #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 101 #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 102 103 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 104 #define CRF_BASE 0xFD1A0000 105 #define CRF_SIZE 0x00600000 106 107 /* CRF registers and bitfields */ 108 #define CRF_RST_APU (CRF_BASE + 0X00000300) 109 110 #define CRF_RST_APU_ACPU_RESET (1 << 0) 111 #define CRF_RST_APU_ACPU_PWRON_RESET (1 << 10) 112 113 #define FPD_MAINCCI_BASE 0xFD000000 114 #define FPD_MAINCCI_SIZE 0x00100000 115 116 /* APU registers and bitfields */ 117 #define FPD_APU_BASE 0xFD5C0000U 118 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 119 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 120 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 121 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 122 123 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 124 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 125 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 126 127 /* PMC registers and bitfields */ 128 #define PMC_GLOBAL_BASE 0xF1110000U 129 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 130 131 /* IPI registers and bitfields */ 132 #define IPI0_REG_BASE U(0xFF330000) 133 #define IPI0_TRIG_BIT (1U << 2U) 134 #define PMC_IPI_TRIG_BIT (1U << 1U) 135 #define IPI1_REG_BASE U(0xFF340000) 136 #define IPI1_TRIG_BIT (1U << 3U) 137 #define IPI2_REG_BASE U(0xFF350000) 138 #define IPI2_TRIG_BIT (1U << 4U) 139 #define IPI3_REG_BASE U(0xFF360000) 140 #define IPI3_TRIG_BIT (1U << 5U) 141 #define IPI4_REG_BASE U(0xFF370000) 142 #define IPI4_TRIG_BIT (1U << 5U) 143 #define IPI5_REG_BASE U(0xFF380000) 144 #define IPI5_TRIG_BIT (1U << 6U) 145 146 #endif /* VERSAL_DEF_H */ 147