1 /*
2 * FreeRTOS Kernel V10.2.0
3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * http://www.FreeRTOS.org
24 * http://aws.amazon.com/freertos
25 *
26 * 1 tab == 4 spaces!
27 */
28
29 /* Standard includes. */
30 #include <stdlib.h>
31
32 /* Scheduler includes. */
33 #include "FreeRTOS.h"
34 #include "task.h"
35
36 #ifndef configSETUP_TICK_INTERRUPT
37 # error configSETUP_TICK_INTERRUPT() must be defined. See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
38 #endif /* configSETUP_TICK_INTERRUPT */
39
40 /* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
41 portmacro.h. */
42 #ifndef configCLEAR_TICK_INTERRUPT
43 # define configCLEAR_TICK_INTERRUPT()
44 #endif
45
46 /* A critical section is exited when the critical section nesting count reaches
47 this value. */
48 #define portNO_CRITICAL_NESTING ((size_t)0)
49
50 /* Tasks are not created with a floating point context, but can be given a
51 floating point context after they have been created. A variable is stored as
52 part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
53 does not have an FPU context, or any other value if the task does have an FPU
54 context. */
55 #define portNO_FLOATING_POINT_CONTEXT ((StackType_t)0)
56
57 /* Constants required to setup the initial task context. */
58 #define portSP_ELx ((StackType_t)0x01)
59 #define portSP_EL0 ((StackType_t)0x00)
60
61 #define portEL1 ((StackType_t)0x04)
62 #define portEL3 ((StackType_t)0x0C)
63 #if 0
64 # define portINITIAL_PSTATE (portEL1 | portSP_EL0)
65 #else
66 # define portINITIAL_PSTATE (portEL3 | portSP_EL0)
67 #endif
68
69 /* Masks all bits in the APSR other than the mode bits. */
70 #define portAPSR_MODE_BITS_MASK (0x0C)
71
72 /* Used in the ASM code. */
73 __attribute__((used)) const uint64_t ulCORE0_INT_SRC = 0x40000060;
74
75 /*-----------------------------------------------------------*/
76
77 /*
78 * Starts the first task executing. This function is necessarily written in
79 * assembly code so is implemented in portASM.s.
80 */
81 extern void vPortRestoreTaskContext(void);
82
83 /*-----------------------------------------------------------*/
84
85 /* A variable is used to keep track of the critical section nesting. This
86 variable has to be stored as part of the task context and must be initialised to
87 a non zero value to ensure interrupts don't inadvertently become unmasked before
88 the scheduler starts. As it is stored as part of the task context it will
89 automatically be set to 0 when the first task is started. */
90 volatile uint64_t ullCriticalNesting = 9999ULL;
91
92 /* Saved as part of the task context. If ullPortTaskHasFPUContext is non-zero
93 then floating point context must be saved and restored for the task. */
94 uint64_t ullPortTaskHasFPUContext = pdFALSE;
95
96 /* Set to 1 to pend a context switch from an ISR. */
97 uint64_t ullPortYieldRequired = pdFALSE;
98
99 /* Counts the interrupt nesting depth. A context switch is only performed if
100 if the nesting depth is 0. */
101 uint64_t ullPortInterruptNesting = 0;
102
103 /*-----------------------------------------------------------*/
104 /*
105 * See header file for description.
106 */
pxPortInitialiseStack(StackType_t * pxTopOfStack,TaskFunction_t pxCode,void * pvParameters)107 StackType_t *pxPortInitialiseStack(
108 StackType_t *pxTopOfStack,
109 TaskFunction_t pxCode,
110 void *pvParameters)
111 {
112 /* Setup the initial stack of the task. The stack is set exactly as
113 expected by the portRESTORE_CONTEXT() macro. */
114
115 /* First all the general purpose registers. */
116 pxTopOfStack--;
117 *pxTopOfStack = 0x0101010101010101ULL; /* R1 */
118 pxTopOfStack--;
119 *pxTopOfStack = (StackType_t)pvParameters; /* R0 */
120 pxTopOfStack--;
121 *pxTopOfStack = 0x0303030303030303ULL; /* R3 */
122 pxTopOfStack--;
123 *pxTopOfStack = 0x0202020202020202ULL; /* R2 */
124 pxTopOfStack--;
125 *pxTopOfStack = 0x0505050505050505ULL; /* R5 */
126 pxTopOfStack--;
127 *pxTopOfStack = 0x0404040404040404ULL; /* R4 */
128 pxTopOfStack--;
129 *pxTopOfStack = 0x0707070707070707ULL; /* R7 */
130 pxTopOfStack--;
131 *pxTopOfStack = 0x0606060606060606ULL; /* R6 */
132 pxTopOfStack--;
133 *pxTopOfStack = 0x0909090909090909ULL; /* R9 */
134 pxTopOfStack--;
135 *pxTopOfStack = 0x0808080808080808ULL; /* R8 */
136 pxTopOfStack--;
137 *pxTopOfStack = 0x1111111111111111ULL; /* R11 */
138 pxTopOfStack--;
139 *pxTopOfStack = 0x1010101010101010ULL; /* R10 */
140 pxTopOfStack--;
141 *pxTopOfStack = 0x1313131313131313ULL; /* R13 */
142 pxTopOfStack--;
143 *pxTopOfStack = 0x1212121212121212ULL; /* R12 */
144 pxTopOfStack--;
145 *pxTopOfStack = 0x1515151515151515ULL; /* R15 */
146 pxTopOfStack--;
147 *pxTopOfStack = 0x1414141414141414ULL; /* R14 */
148 pxTopOfStack--;
149 *pxTopOfStack = 0x1717171717171717ULL; /* R17 */
150 pxTopOfStack--;
151 *pxTopOfStack = 0x1616161616161616ULL; /* R16 */
152 pxTopOfStack--;
153 *pxTopOfStack = 0x1919191919191919ULL; /* R19 */
154 pxTopOfStack--;
155 *pxTopOfStack = 0x1818181818181818ULL; /* R18 */
156 pxTopOfStack--;
157 *pxTopOfStack = 0x2121212121212121ULL; /* R21 */
158 pxTopOfStack--;
159 *pxTopOfStack = 0x2020202020202020ULL; /* R20 */
160 pxTopOfStack--;
161 *pxTopOfStack = 0x2323232323232323ULL; /* R23 */
162 pxTopOfStack--;
163 *pxTopOfStack = 0x2222222222222222ULL; /* R22 */
164 pxTopOfStack--;
165 *pxTopOfStack = 0x2525252525252525ULL; /* R25 */
166 pxTopOfStack--;
167 *pxTopOfStack = 0x2424242424242424ULL; /* R24 */
168 pxTopOfStack--;
169 *pxTopOfStack = 0x2727272727272727ULL; /* R27 */
170 pxTopOfStack--;
171 *pxTopOfStack = 0x2626262626262626ULL; /* R26 */
172 pxTopOfStack--;
173 *pxTopOfStack = 0x2929292929292929ULL; /* R29 */
174 pxTopOfStack--;
175 *pxTopOfStack = 0x2828282828282828ULL; /* R28 */
176 pxTopOfStack--;
177 *pxTopOfStack = (StackType_t)0x00; /* XZR */
178 /* - has no effect, used so there are an even number of registers. */
179 pxTopOfStack--;
180 *pxTopOfStack = (StackType_t)0x00; /* R30 */
181 /* - procedure call link register. */
182 pxTopOfStack--;
183
184 *pxTopOfStack = portINITIAL_PSTATE;
185 pxTopOfStack--;
186
187 *pxTopOfStack = (StackType_t)pxCode; /* Exception return address. */
188 pxTopOfStack--;
189
190 /* The task will start with a critical nesting count of 0 as interrupts are
191 enabled. */
192 *pxTopOfStack = portNO_CRITICAL_NESTING;
193 pxTopOfStack--;
194
195 /* The task will start without a floating point context. A task that uses
196 the floating point hardware must call vPortTaskUsesFPU() before executing
197 any floating point instructions. */
198 *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
199
200 return pxTopOfStack;
201 }
202 /*-----------------------------------------------------------*/
203
xPortStartScheduler(void)204 BaseType_t xPortStartScheduler(void)
205 {
206 uint32_t ulAPSR;
207
208 /* At the time of writing, the BSP only supports EL3. */
209 __asm volatile("MRS %0, CurrentEL" : "=r"(ulAPSR));
210 ulAPSR &= portAPSR_MODE_BITS_MASK;
211
212 configASSERT(ulAPSR == portEL3);
213 if (ulAPSR == portEL3) {
214 {
215 /* Interrupts are turned off in the CPU itself to ensure a tick does
216 not execute while the scheduler is being started. Interrupts are
217 automatically turned back on in the CPU when the first task starts
218 executing. */
219 portDISABLE_INTERRUPTS();
220
221 /* Start the timer that generates the tick ISR. */
222 configSETUP_TICK_INTERRUPT();
223
224 /* Start the first task executing. */
225 vPortRestoreTaskContext();
226 }
227 }
228
229 return 0;
230 }
231 /*-----------------------------------------------------------*/
232
vPortEndScheduler(void)233 void vPortEndScheduler(void)
234 {
235 /* Not implemented in ports where there is nothing to return to.
236 Artificially force an assert. */
237 configASSERT(ullCriticalNesting == 1000ULL);
238 }
239 /*-----------------------------------------------------------*/
240
vPortEnterCritical(void)241 void vPortEnterCritical(void)
242 {
243 portDISABLE_INTERRUPTS();
244
245 /* Now interrupts are disabled ullCriticalNesting can be accessed
246 directly. Increment ullCriticalNesting to keep a count of how many times
247 portENTER_CRITICAL() has been called. */
248 ullCriticalNesting++;
249
250 /* This is not the interrupt safe version of the enter critical function so
251 assert() if it is being called from an interrupt context. Only API
252 functions that end in "FromISR" can be used in an interrupt. Only assert if
253 the critical nesting count is 1 to protect against recursive calls if the
254 assert function also uses a critical section. */
255 if (ullCriticalNesting == 1ULL) {
256 configASSERT(ullPortInterruptNesting == 0);
257 }
258 }
259 /*-----------------------------------------------------------*/
260
vPortExitCritical(void)261 void vPortExitCritical(void)
262 {
263 if (ullCriticalNesting > portNO_CRITICAL_NESTING) {
264 /* Decrement the nesting count as the critical section is being
265 exited. */
266 ullCriticalNesting--;
267
268 /* If the nesting level has reached zero then all interrupt
269 priorities must be re-enabled. */
270 if (ullCriticalNesting == portNO_CRITICAL_NESTING) {
271 /* Critical nesting has reached zero so interrupts
272 should be enabled. */
273 portENABLE_INTERRUPTS();
274 }
275 }
276 }
277 /*-----------------------------------------------------------*/
278
FreeRTOS_Tick_Handler(void)279 void FreeRTOS_Tick_Handler(void)
280 {
281 /* Interrupts should not be enabled before this point. */
282 #if (configASSERT_DEFINED == 1)
283 {
284 uint32_t ulMaskBits;
285
286 __asm volatile("mrs %0, daif" : "=r"(ulMaskBits)::"memory");
287 configASSERT((ulMaskBits & portDAIF_I) != 0);
288 }
289 #endif /* configASSERT_DEFINED */
290
291 /* Ok to enable interrupts after the interrupt source has been cleared. */
292 configCLEAR_TICK_INTERRUPT();
293 portENABLE_INTERRUPTS();
294
295 /* Increment the RTOS tick. */
296 if (xTaskIncrementTick() != pdFALSE) {
297 ullPortYieldRequired = pdTRUE;
298 }
299 }
300